MOTOROLA MC74HCT374AFL1, MC74HCT374AH, MC74HCT374AN, MC74HCT374ADWR2, MC74HCT374AF Datasheet
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MC74HCT374A
Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
High±Performance Silicon±Gate CMOS
The MC74HCT374A may be used as a level converter for interfacing TTL or NMOS outputs to High±Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip±flops, but when Output Enable is high, the outputs are forced to the high±impedance state. Thus, data may be stored even when the outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs.
•Output Drive Capability: 15 LSTTL Loads
•TTL/NMOS±Compatible Input Levels
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 4.5 to 5.5 V
•Low Input Current: 1.0 μA
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 276 FETs or 69 Equivalent Gates
•Improvements over HCT374
ÐImproved Propagation Delays
Ð50% Lower Quiescent Power
ÐImproved Input Noise and Latchup Immunity
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MARKING |
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DIAGRAMS |
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20 |
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PDIP±20 |
MC74HCT374AN |
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N SUFFIX |
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AWLYYWW |
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20 |
CASE 738 |
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1 |
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1 |
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20 |
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SOIC WIDE±20 |
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HCT374A |
20 |
DW SUFFIX |
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AWLYYWW |
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CASE 751D |
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20 |
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TSSOP±20 |
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HCT |
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DT SUFFIX |
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374A |
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CASE 948G |
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ALYW |
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A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device |
Package |
Shipping |
MC74HCT374AN |
PDIP±20 |
1440 / Box |
MC74HCT374ADW |
SOIC±WIDE |
38 / Rail |
MC74HCT374ADWR2 |
SOIC±WIDE |
1000 / Reel |
MC74HCT374ADT |
TSSOP±20 |
75 / Rail |
MC74HCT374ADTR2 |
TSSOP±20 |
2500 / Reel |
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 8 |
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MC74HCT374A/D |
MC74HCT374A
PIN ASSIGNMENT
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OUTPUT |
1 |
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20 |
VCC |
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ENABLE |
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Q0 |
2 |
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19 |
Q7 |
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LOGIC DIAGRAM |
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D0 |
3 |
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18 |
D7 |
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D0 |
3 |
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2 |
Q0 |
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D1 |
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17 |
D6 |
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4 |
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5 |
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Q1 |
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16 |
Q6 |
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D1 |
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Q1 |
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Q2 |
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15 |
Q5 |
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D2 |
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Q2 |
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D2 |
7 |
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14 |
D5 |
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8 |
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9 |
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DATA |
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D3 |
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Q3 |
NONINVERTING |
D3 |
8 |
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13 |
D4 |
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13 |
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INPUTS |
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12 |
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D4 |
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Q4 |
OUTPUTS |
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14 |
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15 |
Q3 |
9 |
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12 |
Q4 |
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D5 |
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Q5 |
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17 |
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16 |
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GND |
10 |
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11 |
CLOCK |
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D6 |
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Q6 |
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18 |
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19 |
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D7 |
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Q7 |
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11 |
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FUNCTION TABLE |
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CLOCK |
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Inputs |
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Output |
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PIN 20 = VCC |
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Output |
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1 |
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Enable |
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Clock |
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D |
Q |
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OUTPUT ENABLE |
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PIN 10 = GND |
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L |
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H |
H |
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L |
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L |
L |
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L |
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L,H, |
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X |
No Change |
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H |
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X |
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X |
Z |
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X = don't care |
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Z = high impedance |
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Design Criteria |
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Value |
Units |
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Internal Gate Count* |
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69 |
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ea. |
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Internal Gate Propagation Delay |
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1.5 |
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ns |
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Internal Gate Power Dissipation |
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5.0 |
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μW |
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Speed Power Product |
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.0075 |
pJ |
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*Equivalent to a two±input NAND gate.
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MC74HCT374A
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
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Vin |
DC Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Iin |
DC Input Current, per Pin |
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± 20 |
mA |
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Iout |
DC Output Current, per Pin |
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± 35 |
mA |
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ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
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PD |
Power Dissipation in Still Air, |
Plastic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
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± 65 to + 150 |
_C |
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TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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(Plastic DIP, SOIC, SSOP or TSSOP Package) |
260 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C
TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
4.5 |
5.5 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
TA |
Operating Temperature, All Package Types |
± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time (Figure 1) |
0 |
500 |
ns |
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
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± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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VIH |
Minimum High±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
4.5 |
2.0 |
2.0 |
2.0 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
2.0 |
2.0 |
2.0 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
4.5 |
0.8 |
0.8 |
0.8 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
0.8 |
0.8 |
0.8 |
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VOH |
Minimum High±Level Output |
Vin = VIH or VIL |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
5.4 |
5.4 |
5.4 |
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Vin = VIH or VIL |
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|Iout| v 6.0 mA |
4.5 |
3.98 |
3.84 |
3.7 |
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VOL |
Maximum Low±Level Output |
Vin = VIH or VIL |
4.5 |
0.1 |
0.1 |
0.1 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
0.1 |
0.1 |
0.1 |
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Vin = VIH or VIL |
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|Iout| v 6.0 mA |
4.5 |
0.26 |
0.33 |
0.4 |
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Iin |
Maximum Input Leakage |
Vin = VCC or GND |
5.5 |
± 0.1 |
± 1.0 |
± 1.0 |
μA |
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Current |
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IOZ |
Maximum Three±State |
Output in High±Impedance State |
5.5 |
± 0.5 |
± 5.0 |
± 10 |
μA |
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Leakage Current |
Vin = VIL or VIH |
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Vout = VCC or GND |
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ICC |
Maximum Quiescent Supply |
Vin = VCC or GND |
5.5 |
4.0 |
40 |
160 |
μA |
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Current (per Package) |
Iout = 0 μA |
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