MOTOROLA MC74ACT573DW, MC74ACT573DWR2, MC74ACT573M, MC74ACT573MEL, MC74ACT573DTEL Datasheet

Octal D Type Latch with 3 State Outputs

The MC74AC573/74ACT573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.

The MC74AC573/74ACT573 is functionally identical to the MC74AC373/ 74ACT373 but has inputs and outputs on opposite sides.

•Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors

•Useful as Input or Output Port for Microprocessors

•Functionally Identical to MC74AC373/74ACT373

•3-State Outputs for Bus Interfacing

•Outputs Source/Sink 24 mA

•′ACT573 Has TTL Compatible Inputs

VCC			O0		O1		O2		O3		O4		O5		O6		O7		LE
	20		19		18		17		16		15		14		13		12		11

1

2

3

4

5

6

7

8

9

10

OE

D0

D1

D2

D3

D4

D5

D6

D7

GND

PIN NAMES

D0±D7

Data Inputs

LE

Latch Enable Input

OE

3-State Output Enable Input

O0±O7

3-State Latch Outputs

TRUTH TABLE

	Inputs		Outputs
OE	LE	Dn	On
L	H	H	H
L	H	L	H
L	L	X	O0
H	X	X	Z

H = HIGH Voltage Level

L = LOW Voltage Level

Z = High Impedance

X = Immaterial

O0 = Previous O0 before LOW-to-HIGH Transition of Clock

MC74AC573

MC74ACT573

OCTAL D-TYPE

LATCH WITH

3-STATE OUTPUTS

N SUFFIX

CASE 738-03

PLASTIC

DW SUFFIX

CASE 751D-04

PLASTIC

LOGIC SYMBOL

D0 D1 D2 D3 D4 D5 D6 D7 LE

OE

O0 O1 O2 O3 O4 O5 O6 O7

FACT DATA

5-1

MC74AC573 MC74ACT573

FUNCTIONAL DESCRIPTION

The MC74AC573/74ACT574 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D

inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

			LOGIC DIAGRAM
D0	D1	D2	D3	D4	D5	D6	D7
D	D	D	D	D		D	D	D
Q	Q	Q	Q	Q		Q	Q	Q
LE	LE	LE	LE	LE		LE	LE	LE
LE
OE
	O0	O1	O2	O3	O4	O5	O6	O7

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

FACT DATA

5-2

MC74AC573 MC74ACT573

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	±0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Vout	DC Output Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Iin	DC Input Current, per Pin	±20	mA
Iout	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC VCC or GND Current per Output Pin	±50	mA
Tstg	Storage Temperature	±65 to +150	°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

	Symbol	Parameter		Min	Typ	Max	Unit
	VCC	Supply Voltage	′AC	2.0	5.0	6.0	V
			′ACT	4.5	5.0	5.5
	Vin, Vout	DC Input Voltage, Output Voltage (Ref. to GND)		0		VCC	V
		Input Rise and Fall Time (Note 1)	VCC @ 3.0 V		150
	tr, tf		VCC @ 4.5 V		40		ns/V
		′AC Devices except Schmitt Inputs
			VCC @ 5.5 V		25
	tr, tf	Input Rise and Fall Time (Note 2)	VCC @ 4.5 V		10		ns/V
		′ACT Devices except Schmitt Inputs	VCC @ 5.5 V		8.0
	TJ	Junction Temperature (PDIP)				140	°C
	TA	Operating Ambient Temperature Range		±40	25	85	°C
	IOH	Output Current Ð High				±24	mA
	IOL	Output Current Ð Low				24	mA

1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

FACT DATA

5-3