MOTOROLA MC74HC174AFR2, MC74HC174AFEL, MC74HC174AFL1, MC74HC174AFL2, MC74HC174ADTR2 Datasheet

MC74HC174A

Hex D Flip-Flop with Common Clock and Reset

High±Performance Silicon±Gate CMOS

The MC74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of six D flip±flops with common Clock and Reset inputs. Each flip±flop is loaded with a low±to±high transition of the Clock input. Reset is asynchronous and active±low.

•Output Drive Capability: 10 LSTTL Loads

•TTL NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 162 FETs or 40.5 Equivalent Gates

LOGIC DIAGRAM

D0

3

2

Q0

D1

4

5

Q1

DATA

D2

6

7

Q2

NONINVERTING

INPUTS

D3

11

10

Q3

OUTPUTS

D4

13

12

Q4

D5

14

15

Q5

CLOCK

9

PIN 16 = VCC

1

PIN 8 = GND

RESET

FUNCTION TABLE

Inputs

Output

Reset

Clock

D

Q

L

X

X

L

H

H

H

H

L

L

H

L

X

No Change

H

X

No Change

Design Criteria

Value

Units

Internal Gate Count*

40.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

μW

Speed Power Product

.0075

pJ

*Equivalent to a two±input NAND gate.

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			MARKING
			DIAGRAMS
			16
	PDIP±16		MC74HC174AN
	N SUFFIX
16			AWLYYWW
	CASE 648
1			1
			16
	SO±16		HC174A
	D SUFFIX
16			AWLYWW
	CASE 751B
1
			1
A	= Assembly Location
WL	= Wafer Lot
YY	= Year
WW = Work Week
PIN ASSIGNMENT
RESET	1	16	VCC
Q0	2	15	Q5
D0	3	14	D5
D1	4	13	D4
Q1	5	12	Q4
D2	6	11	D3
Q2	7	10	Q3
GND	8	9	CLOCK

ORDERING INFORMATION

Device	Package	Shipping
MC74HC174AN	PDIP±16	2000 / Box
MC74HC174AD	SOIC±16	48 / Rail
MC74HC174ADR2	SOIC±16	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 7		MC74HC174A/D

MC74HC174A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)		±0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	VCC = 2.0 V	0	1000	ns
		VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA	4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA	4.5	1.35	1.35	1.35
			6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9
		Vin = VIH or VIL
		|Iout| v 4.0 mA	4.5	3.98	3.84	3.7
		|Iout| v 5.2 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 4.0 mA	4.5	0.26	0.33	0.4
		|Iout| v 5.2 mA	6.0	0.26	0.33	0.4

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MC74HC174A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTES:

1.Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

2.Total Supply Current = ICC + S ICC.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to	v _		v	_
Symbol	Parameter	V	_		C			Unit
			25 C	85			125 C
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	6.0	4.8			4.0	MHz
	(Figures 1 and 4)	4.5	30	24			20
		6.0	35	28			24
tPLH	Maximum Propagation Delay, Clock to Q	2.0	110	140			165	ns
tPHL	(Figures 1 and 4)	4.5	22	28			33
		6.0	19	24			28
tPLH	Maximum Propagation Delay, Reset to Q	2.0	110	140			160	ns
tPHL	(Figures 2 and 4)	4.5	21	28			32
		6.0	19	24			27
tTLH	Maximum Output Transition Time, Any Output	2.0	75	95			110	ns
tTHL	(Figures 1 and 4)	4.5	15	19			22
		6.0	13	16			19
Cin	Maximum Input Capacitance		10	10			10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	62	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

						Guaranteed Limit
			VCC	± 55 to 25_C			v 85_C			v 125_C
Symbol	Parameter	Fig.	V	Min	Max		Min	Max		Min	Max	Unit
tsu	Minimum Setup Time, Data to Clock	3	2.0	50			65			75		ns
			4.5	10			13			15
			6.0	9.0			11			13
th	Minimum Hold Time, Clock to Data	3	2.0	5.0			5.0			5.0		ns
			4.5	5.0			5.0			5.0
			6.0	5.0			5.0			5.0
trec	Minimum Recovery Time, Reset Inactive to	2	2.0	5.0			5.0			5.0		ns
	Clock		4.5	5.0			5.0			5.0
			6.0	5.0			5.0			5.0
tw	Minimum Pulse Width, Clock	1	2.0	75			95			110		ns
			4.5	15			19			22
			6.0	13			16			19
tw	Minimum Pulse Width, Reset	2	2.0	75			95			110		ns
			4.5	15			19			22
			6.0	13			16			19
tr, tf	Maximum Input Rise and Fall Times	1	2.0		1000			1000			1000	ns
			4.5		500			500			500
			6.0		400			400			400

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