MOTOROLA MC74HCT245AFL1, MC74HCT245AH, MC74HCT245AN, MC74HCT245ADWR2, MC74HCT245ADT Datasheet

MC74HCT245A

Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT245A is identical in pinout to the LS245. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

The MC74HCT245A is a 3±state noninverting transceiver that is used for 2±way asynchronous communication between data buses. The device has an active±low Output Enable pin, which is used to place the I/O ports into high±impedance states. The Direction control determines whether data flows from A to B or from B to A.

•Output Drive Capability: 15 LSTTL Loads

•TTL/NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 304 FETs or 76 Equivalent Gates

LOGIC DIAGRAM

		A1	2		18	B1
		A2	3		17	B2
		A3	4		16	B3
A		A4	5		15	B4	B
DATA		A5	6		14	B5	DATA
PORT							PORT
			7		13
		A6				B6
		A7	8		12	B7
		A8	9		11	B8
DIRECTION			1		PIN 20 = V
			19			CC
OUTPUT ENABLE					PIN 10 = GND
Design Criteria				Value	Units
Internal Gate Count*				76	ea
Internal Gate Propagation Delay				1.0	ns
Internal Gate Power Dissipation				5.0	μW
Speed Power Product				0.005	pJ
*Equivalent to a two±input NAND gate.
			FUNCTION TABLE
Control Inputs
Output
Enable	Direction			Operation
L		L	Data Transmitted from Bus B to Bus A
L		H	Data Transmitted from Bus A to Bus B
H		X	Buses Isolated (High±Impedance State)

X = Don't Care

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			MARKING
		DIAGRAMS
		20
	PDIP±20	MC74HCT245AN
	N SUFFIX
			AWLYYWW
20	CASE 738
1		1
		20
SOIC WIDE±20			HCT245A
20	DW SUFFIX
			AWLYYWW
1	CASE 751D
		1	20
	TSSOP±20		HCT
20	DT SUFFIX		245A
1	CASE 948G		ALYW
			1
A	= Assembly Location
WL	= Wafer Lot
YY	= Year

WW = Work Week

PIN ASSIGNMENT

DIRECTION		1	20	VCC
A1		2	19	OUTPUT ENABLE
A2		3	18	B1
A3		4	17	B2
A4		5	16	B3
A5		6	15	B4
A6		7	14	B5
A7		8	13	B6
A8		9	12	B7
GND		10	11	B8

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT245AN	PDIP±20	1440 / Box
MC74HCT245ADW	SOIC±WIDE	38 / Rail
MC74HCT245ADWR2	SOIC±WIDE	1000 / Reel
MC74HCT245ADT	TSSOP±20	75 / Rail
MC74HCT245ADTR2	TSSOP±20	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HCT245A/D

MC74HCT245A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, SOIC, SSOP or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2.0	2.0	2.0	V
	Voltage	|Iout| v 20 μA	5.5	2.0	2.0	2.0
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8	0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8	0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4	4.4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4	5.4
		Vin = VIH or VIL
		|Iout| v 6.0 mA	4.5	3.98	3.84	3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
Iin	Maximum Input Leakage Current	Vin = VCC or GND, Pins 1 or 19	5.5	± 0.1	± 1.0	± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA
IOZ	Maximum Three±State	Output in High±Impedance State	5.5	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND, I/O Pins

ICC	Additional Quiescent Supply	Vin = 2.4 V, Any One Input		≥	±55_C	25_C to 125_C
	Current	Vin = VCC or GND, Other Inputs
		lout = 0 μA	5.5		2.9	2.4	mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HCT245A

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		± 55 to
Symbol	Parameter	25_C		v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, A to B or B to A	22		28	33	ns
tPHL	(Figures 1 and 3)
tPLZ,	Maximum Propagation Delay, Direction or Output Enable to A or B	30		36	42	ns
tPHZ	(Figures 2 and 4)
tPZL,	Maximum Propagation Delay, Output Enable to A or 8	30		36	42	ns
tPZH	(Figures 2 and 4)
tTLH,	Maximum Output Transition Time. any Output	12		15	18	ns
tTHL	(Figures 1 and 3)
Cin	Maximum Input Capacitance (Pin 1 or 19)	10		10	10	pF
Cout	Maximum Three±State I/O Capacitance, (I/O in High±Impedance	15		15	15	pF
	State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	97	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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