MOTOROLA MC74HC390DR2, MC74HC390N, MC74HC390FR2, MC74HC390F, MC74HC390FEL Datasheet

...

0 (0)



SEMICONDUCTOR TECHNICAL DATA

REV 6

 Motorola, Inc. 1995

10/95

$ # !&   $#! %#

  ÷  #"

High–Performance Silicon–Gate CMOS

The MC54/74HC390 is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 4–bit counters, each composed of a divide–by–two and a divide–by–five section. The divide–by–two and divide–by–five counters have separate clock inputs, and can be cascaded to implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–low transitions of the clock input. A separate, asynchronous reset is provided for each 4–bit counter. State changes of the Q outputs d o not occur s imultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No 7A

• Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

1, 15

4, 12

2, 14

3, 13

5, 11 6, 10

7, 9

PIN 16 = V

PIN 8 = GND

CLOCK A

RESET

CLOCK B

COUNTER



PIN ASSIGNMENT

125

CLOCK B

RESET b

CLOCK A

CLOCK B

RESET a

CLOCK A

GND

FUNCTION TABLE

Clock

A B Reset Action

X X H Reset

÷ 2 and ÷ 5

X L Increment

÷ 2

X L Increment

÷ 5

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXJ MC74HCXXXN MC74HCXXXD

Ceramic Plastic SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

MC54/74HC390

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

DC Input Current, per Pin

± 20

out

DC Output Current, per Pin

± 25

DC Supply Current, VCC and GND Pins

± 50

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750 500

stg

Storage Temperature

– 65 to + 150

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic or SOIC DIP)

(Ceramic DIP)

260 300

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage (Referenced to GND)

2.0

6.0

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

– 55

+ 125

tr, t

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0 0 0

1000

500 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

CC V

– 55 to

25_C

85_Cv 125_C

Unit

Minimum High–Level Input Voltage

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

Maximum Low–Level Input Voltage

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

Minimum High–Level Output Voltage

Vin = VIH or V

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL|I

out

| v 4.0 mA

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

Maximum Low–Level Output Voltage

Vin = VIH or V

out

| v 20 µA

2.0

4.5

6.0

0.1

Vin = VIH or VIL|I

out

| v 4.0 mA

out

| v 5.2 mA

4.5

6.0

0.26

0.33

0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

µA

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

out

= 0 µA

6.0

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HC390

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tf = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

CC V

– 55 to

25_C

85_Cv 125_C

Unit

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

2.0

4.5

6.0

5.4 27 32

4.4 22 26

3.6 18 21

MHz

PLH

PHL

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

2.0

4.5

6.0

120

24 20

150

30 26

180

36 31

PLH

PHL

Maximum Propagation Delay, Clock A to QC (QA connected to Clock B)

(Figures 1 and 3)

2.0

4.5

6.0

290

58 49

365

73 62

435

87 74

PLH

PHL

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

2.0

4.5

6.0

130

26 22

165

33 28

195

39 33

PLH

PHL

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

2.0

4.5

6.0

185

37 31

230

46 39

280

56 48

PLH

PHL

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

2.0

4.5

6.0

130

26 22

165

33 28

195

39 33

PHL

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

2.0

4.5

6.0

165

33 28

205

41 35

250

50 43

TLH

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

75 15 13

95 19 16

110

22 19

Maximum Input Capacitance

—

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

Power Dissipation Capacitance (Per Counter)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

CC V

– 55 to

25_C

85_Cv 125_C

Unit

rec

Minimum Recovery Time, Reset Inactive to Clock A or Clock B

(Figure 2)

2.0

4.5

6.0

50 10

65 13 11

75 15 13

Minimum Pulse Width, Clock A, Clock B

(Figure 1)

2.0

4.5

6.0

80 16 14

100

20 17

120

24 20

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

125

25 21

155

31 26

190

38 32

tf, t

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500 400

1000

500 400

1000

500 400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

+ 5 hidden pages