MOTOROLA MC74HC126AF, MC74HC126AFEL, MC74HC126AFL1, MC74HC126AD, MC74HC126ADR2 Datasheet

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MC74HC125A,

MC74HC126A

Quad 3-State Noninverting

Buffers

High±Performance Silicon±Gate CMOS

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC125A and HC126A noninverting buffers are designed to be used with 3±state memory address drivers, clock drivers, and other bus±oriented systems. The devices have four separate output enables that are active±low (HC125A) or active±high (HC126A).

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 72 FETs or 18 Equivalent Gates

HC125A

LOGIC DIAGRAM

HC126A

Active±Low Output Enables

Active±High Output Enables

OE1

OE2

OE3

OE4

PIN 14 = VCC

PIN 7 = GND

FUNCTION TABLE

HC125A

HC126A

Inputs

Output

Inputs

Output

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			MARKING
			DIAGRAMS
			14
	PDIP±14		MC74HC12xAN
	N SUFFIX		MC74HC12xAN
	N SUFFIX		AWLYYWW
	CASE 646		AWLYYWW
			1
			14
	SOIC±14		HC12xA
	D SUFFIX		HC12xA
	D SUFFIX		AWLYWW
CASE 751A			AWLYWW
CASE 751A
			1
			14
	TSSOP±14		HC
	DT SUFFIX		12xA
	CASE 948G		ALYW
			1
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
PIN ASSIGNMENT
OE1	1	14	VCC
A1	2	13	OE4
Y1	3	12	A4
OE2	4	11	Y4
A2	5	10	OE3
Y2	6	9	A3
GND	7	8	Y3

ORDERING INFORMATION

Device	Package	Shipping
MC74HC12xAN	PDIP±14	2000 / Box
MC74HC12xAD	SOIC±14	55 / Rail
MC74HC12xADR2	SOIC±14	2500 / Reel
MC74HC12xADT	TSSOP±14	96 / Rail
MC74HC12xADTR2	TSSOP±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 9		MC74HC125A/D

MC74HC125A, MC74HC126A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit

VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 35	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450

Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit

VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage		0	VCC	V
	(Referenced to GND)

TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit

				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit

VIH	Minimum High±Level Input	Vout = VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	\|Iout\| v 20	μA	3.0	2.1	2.1	2.1
				4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2

VIL	Maximum Low±Level Input	Vout = 0.1 V		2.0	0.5	0.5	0.5	V
	Voltage	\|Iout\| v 20 μA		3.0	0.9	0.9	0.9
				4.5	1.35	1.35	1.35
				6.0	1.8	1.8	1.8

VOH	Minimum High±Level Output	Vin = VIH	μA	2.0	1.9	1.9	1.9	V
	Voltage	\|Iout\| v 20	μA	4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9

		Vin = VIH	\|Iout\| v 3.6 mA	3.0	2.48	2.34	2.2
			\|Iout\| v 6.0 mA	4.5	3.98	3.84	3.7
			\|Iout\| v 7.8 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin = VIL	μA	2.0	0.1	0.1	0.1	V
	Voltage	\|Iout\| v 20	μA	4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1

		Vin = VIL	\|Iout\| v 3.6 mA	3.0	0.26	0.33	0.4
			\|Iout\| v 6.0 mA	4.5	0.26	0.33	0.4
			\|Iout\| v 7.8 mA	6.0	0.26	0.33	0.4

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MC74HC125A, MC74HC126A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit

			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current

IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit

tPLH,	Maximum Propagation Delay, Input A to Output Y	2.0	90	115	135	ns
tPHL	(Figures 1 and 3)	3.0	36	45	60
		4.5	18	23	27
		6.0	15	20	23

tPLZ,	Maximum Propagation Delay, Output Enable to Y	2.0	120	150	180	ns
tPHZ	(Figures 2 and 4)	3.0	45	60	80
		4.5	24	30	36
		6.0	20	26	31

tPZL,	Maximum Propagation Delay, Output Enable to Y	2.0	90	115	135	ns
tPZH	(Figures 2 and 4)	3.0	36	45	60
		4.5	18	23	27
		6.0	15	20	23

tTLH,	Maximum Output Transition Time, Any Output	2.0	60	75	90	ns
tTHL	(Figures 1 and 3)	3.0	22	28	34
		4.5	12	15	18
		6.0	10	13	15

Cin	Maximum Input Capacitance	Ð	10	10	10	pF
Cout	Maximum Three±State Output Capacitance	Ð	15	15	15	pF
	(Output in High±Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Buffer)*	30	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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