Hex D Flip Flop with Master Reset
The MC74AC174/74ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.
•Outputs Source/Sink 24 mA
•′ACT174 Has TTL Compatible Inputs
VCC |
Q5 |
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D5 |
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D4 |
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Q4 |
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D3 |
Q3 |
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CP |
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16 |
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15 |
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14 |
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13 |
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12 |
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11 |
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10 |
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9 |
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PIN NAMES |
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D0±D5 |
Data Inputs |
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CP |
Clock Pulse Input |
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1 |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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8 |
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MR |
Master Reset Input |
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MR |
Q0 |
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D0 |
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D1 |
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Q1 |
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D2 |
Q2 |
GND |
Q0±Q5 |
Outputs |
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TRUTH TABLE
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Inputs |
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Output |
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MR |
CP |
D |
Q |
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L |
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X |
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L |
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H |
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H |
H |
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H |
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L |
L |
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H |
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L |
X |
Q |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition of Clock
MC74AC174
MC74ACT174
HEX D FLIP-FLOP
WITH MASTER RESET
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
CPD0 D1 D2 D3 D4 D5
MR
Q0 Q1 Q2 Q3 Q4 Q5
FACT DATA
5-1
MC74AC174 MC74ACT174
FUNCTIONAL DESCRIPTION
The MC74AC174/74ACT174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The MC74AC174/ 74ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
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LOGIC DIAGRAM |
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MR CP D5 |
D4 |
D3 |
D2 |
D1 |
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D0 |
D Q |
D Q |
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D Q |
D Q |
D Q |
D Q |
CP |
CP |
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CP |
CP |
CP |
CP |
CD |
CD |
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CD |
CD |
CD |
CD |
Q5 |
Q4 |
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Q3 |
Q2 |
Q1 |
Q0 |
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
±0.5 to +7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Iin |
DC Input Current, per Pin |
±20 |
mA |
Iout |
DC Output Sink/Source Current, per Pin |
±50 |
mA |
ICC |
DC VCC or GND Current per Output Pin |
±50 |
mA |
Tstg |
Storage Temperature |
±65 to +150 |
°C |
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
FACT DATA
5-2
MC74AC174 MC74ACT174
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
′AC |
2.0 |
5.0 |
6.0 |
V |
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′ACT |
4.5 |
5.0 |
5.5 |
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Vin, Vout |
DC Input Voltage, Output Voltage (Ref. to GND) |
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0 |
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VCC |
V |
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Input Rise and Fall Time (Note 1) |
VCC @ 3.0 V |
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150 |
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tr, tf |
VCC @ 4.5 V |
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40 |
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ns/V |
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′AC Devices except Schmitt Inputs |
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VCC @ 5.5 V |
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25 |
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tr, tf |
Input Rise and Fall Time (Note 2) |
VCC @ 4.5 V |
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10 |
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ns/V |
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′ACT Devices except Schmitt Inputs |
VCC @ 5.5 V |
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8.0 |
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TJ |
Junction Temperature (PDIP) |
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140 |
°C |
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TA |
Operating Ambient Temperature Range |
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±40 |
25 |
85 |
°C |
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IOH |
Output Current Ð High |
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±24 |
mA |
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IOL |
Output Current Ð Low |
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24 |
mA |
1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
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74AC |
74AC |
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Symbol |
Parameter |
VCC |
TA = +25°C |
TA = |
Unit |
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Conditions |
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(V) |
±40°C to +85°C |
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Typ |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
1.5 |
2.1 |
2.1 |
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VOUT = 0.1 V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
3.15 |
V |
or VCC ± 0.1 V |
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5.5 |
2.75 |
3.85 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
1.5 |
0.9 |
0.9 |
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VOUT = 0.1 V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
1.35 |
V |
or VCC ± 0.1 V |
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5.5 |
2.75 |
1.65 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.99 |
2.9 |
2.9 |
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IOUT = ±50 mA |
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Output Voltage |
4.5 |
4.49 |
4.4 |
4.4 |
V |
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5.5 |
5.49 |
5.4 |
5.4 |
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*VIN = VIL or VIH |
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3.0 |
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2.56 |
2.46 |
V |
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±12 mA |
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4.5 |
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3.86 |
3.76 |
IOH |
±24 mA |
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5.5 |
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4.86 |
4.76 |
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±24 mA |
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VOL |
Maximum Low Level |
3.0 |
0.002 |
0.1 |
0.1 |
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IOUT = 50 mA |
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Output Voltage |
4.5 |
0.001 |
0.1 |
0.1 |
V |
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5.5 |
0.001 |
0.1 |
0.1 |
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*VIN = VIL or VIH |
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3.0 |
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0.36 |
0.44 |
V |
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12 mA |
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4.5 |
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0.36 |
0.44 |
IOL |
24 mA |
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5.5 |
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0.36 |
0.44 |
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24 mA |
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IIN |
Maximum Input |
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μ |
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Leakage Current |
5.5 |
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0.1 |
1.0 |
A |
VI = VCC, GND |
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IOLD |
²Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65 V Max |
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Output Current |
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IOHD |
5.5 |
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±75 |
mA |
VOHD = 3.85 V Min |
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ICC |
Maximum Quiescent |
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μ |
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Supply Current |
5.5 |
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8.0 |
80 |
A |
VIN = VCC or GND |
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* All outputs loaded; thresholds on input associated with output under test. ² Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
FACT DATA
5-3
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