Product Preview
9"Bit Register With 3"State Outputs (Non"Inverting)
The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This device has 3-state outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enabled pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the flip-flops. The MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems.
When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
•3-State Outputs for Bus Interfacing
•Broad Side Pin Configuration
•ACT has TTL ± Compatible Inputs
•High Speed Parallel Positive Edge-Triggered D-Type Flip-Flops
•High Performance Bus Interface Buffering for Busses Carrying Parity
•Outputs Source/Sink 24 mA
Pinout: 24-Lead Packages (Top View)
VCC |
O0 |
|
O1 |
|
O2 |
|
O3 |
|
O4 |
|
O5 |
|
O6 |
|
O7 |
|
O8 |
|
EN |
|
CP |
|||
|
24 |
|
23 |
|
22 |
|
21 |
|
20 |
|
19 |
|
18 |
|
17 |
|
16 |
|
15 |
|
14 |
|
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MC74AC823
MC74ACT823
9-BIT REGISTER WITH
3-STATE OUTPUTS
24
1
N SUFFIX
CASE 724-03
PLASTIC PACKAGE
DW SUFFIX
CASE 751E-04
SOIC PACKAGE
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PIN NAMES |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D0 ± D8 |
Data Inputs |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
O0 ± O8 |
Data Outputs |
|
1 |
|
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
|
12 |
|
|
||||||||||
|
|
|
|
|
OE |
Output Enable |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
OE1 |
D0 |
D1 |
D2 |
|
D3 |
D4 |
D5 |
D6 |
D7 |
D8 |
|
CLR |
GND |
|
EN |
|
Clock Enable |
|||||
|
|
|
|
|
|
CLR |
Clear |
||||||||||||||||||
FUNCTION TABLE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CP |
Clock Input |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
Inputs |
|
|
|
|
|
Internal |
|
|
Outputs |
|
|
|
Operating Mode |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OE |
|
CLR |
|
EN |
CP |
|
Dn |
|
|
|
Q |
|
|
O |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
H |
|
X |
|
L |
↑ |
|
L |
|
|
|
L |
|
|
Z |
|
High Z |
|
||||||
|
|
H |
|
X |
|
L |
↑ |
|
H |
|
|
|
H |
|
|
Z |
|
High Z |
|
||||||
|
|
H |
|
L |
|
X |
X |
|
X |
|
|
|
L |
|
|
Z |
|
Clear |
|
||||||
|
|
L |
|
L |
|
X |
X |
|
X |
|
|
|
L |
|
|
L |
|
Clear |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
H |
|
H |
|
H |
X |
|
X |
|
|
|
NC |
|
|
Z |
|
Hold |
|
||||||
|
|
L |
|
H |
|
H |
X |
|
X |
|
|
|
NC |
|
|
NC |
|
Hold |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
H |
|
H |
|
L |
↑ |
|
L |
|
|
|
L |
|
|
Z |
|
Load |
|
||||||
|
|
H |
|
H |
|
L |
↑ |
|
H |
|
|
|
H |
|
|
Z |
|
Load |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
L |
|
H |
|
L |
↑ |
|
L |
|
|
|
L |
|
|
L |
|
Load |
|
||||||
|
|
L |
|
H |
|
L |
↑ |
|
H |
|
|
|
H |
|
|
H |
|
Load |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; Z = High Impedance State; ↑ = LOW-to-High Transition; NC = No Change
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FACT DATA
5-1
MC74AC823 MC74ACT823
LOGIC SYMBOL
O0 O1 O2 O3 O4 O5 O6 O7 O8
CLR
OE 
CP
EN
D0 |
D1 D2 D3 |
D4 D5 |
D6 |
D7 |
D8 |
LOGIC DIAGRAM
EN
CP
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
|
D7 |
D8 |
CP |
CP |
CP |
CP |
CP |
CP |
CP |
|
CP |
CP |
D |
D |
D |
D |
D |
D |
D |
|
D |
D |
Q |
Q |
Q |
|
Q |
Q |
Q |
Q |
Q |
Q |
CLR |
CLR |
CLR |
CLR |
CLR |
CLR |
CLR |
|
CLR |
CLR |
CLR |
|
|
|
|
|
|
|
|
|
OE
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
Q8 |
FACT DATA
5-2
MC74AC823 MC74ACT823
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Units |
|
|
|
|
VCC |
DC Supply Voltage (Referenced to GND) |
±0.5 to +7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
±0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage (Referenced to GND) |
±0.5 to VCC + 0.5 |
V |
Iin |
DC Input Current, per Pin |
± 20 |
mA |
Iout |
DC Output Sink/Source Current, per Pin |
± 50 |
mA |
ICC |
DC VCC or GND Current per Output Pin |
± 50 |
mA |
Tstg |
Storage Temperature Range |
±65 to +150 |
°C |
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
|
Min |
Typ |
Min |
Unit |
|
|
|
|
|
|
|
|
|
VCC |
Supply Voltage |
′AC |
2.0 |
5.0 |
6.0 |
V |
|
|
|
|
|
||||
′ACT |
4.5 |
5.0 |
5.5 |
||||
|
|
|
|||||
|
|
|
|
|
|
|
|
Vin |
DC Input Voltage, Output Voltage (Ref. to GND) |
|
0 |
|
VCC |
V |
|
|
Input Rise and Fall Time (Note 1) |
VCC @ 3.0 V |
|
150 |
|
|
|
t/ v |
VCC @ 4.5 V |
|
40 |
|
ns/V |
||
′AC Devices except Schmitt Inputs |
|
|
|||||
|
|
VCC @ 5.5 V |
|
25 |
|
|
|
tr, tf |
Input Rise and Fall Time (Note 2) |
VCC @ 4.5 V |
|
10 |
|
ns/V |
|
′ACT Devices except Schmitt Inputs |
VCC @ 5.5 V |
|
8.0 |
|
|||
|
|
|
|
|
|||
TJ |
Junction Temperature (PDIP) |
|
|
|
140 |
°C |
|
TA |
Operating Ambient Temperature Range |
|
±40 |
25 |
85 |
°C |
|
IOH |
Output Current Ð HIGH |
|
|
|
±24 |
mA |
|
IOL |
Output Current Ð LOW |
|
|
|
24 |
mA |
1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA
5-3
Loading...