MOTOROLA MC74HCU04ADTEL, MC74HCU04ADTR2, MC74HCU04AF, MC74HCU04AFEL, MC74HCU04AD Datasheet

MC74HCU04A

Hex Unbuffered Inverter

High±Performance Silicon±Gate CMOS

The MC74HCU04A is identical in pinout to the LS04 and the MC14069UB. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of six single±stage inverters. These inverters are well suited for use as oscillators, pulse shapers, and in many other applications requiring a high±input impedance amplifier. For digital applications, the HC04A is recommended.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator Configurations

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 12 FETs or 3 Equivalent Gates

		LOGIC DIAGRAM
1			2
A1					Y1
3			4		Y2
A2
5			6		Y3
A3
							Y =
								A
9			8		Y4
A4
11			10		Y5
A5
13			12				PIN 14 = VCC
					Y6		PIN 7 = GND
A6
		FUNCTION TABLE
		Inputs	Outputs
		A	Y
		L	H
		H	L

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				MARKING
				DIAGRAMS
				14
		PDIP±14		MC74HCU04AN
		N SUFFIX
				AWLYYWW
		CASE 646
				1
				14
		SOIC±14		HCU04A
		D SUFFIX
				AWLYWW
	CASE 751A
				1
				14
		TSSOP±14		HCU
		DT SUFFIX		04A
		CASE 948G		ALYW
				1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	PIN ASSIGNMENT
	A1	1	14	VCC
	Y1	2	13	A6
	A2	3	12	Y6
	Y2	4	11	A5
	A3	5	10	Y5
	Y3	6	9	A4
	GND	7	8	Y4

ORDERING INFORMATION

Device	Package	Shipping
MC74HCU04AN	PDIP±14	2000 / Box
MC74HCU04AD	SOIC±14	55 / Rail
MC74HCU04ADR2	SOIC±14	2500 / Reel
MC74HCU04ADT	TSSOP±14	96 / Rail
MC74HCU04ADTR2	TSSOP±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 2		MC74HCU04A/D

MC74HCU04A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ±10mW/ _C from 65_ to 125_C SOIC Package: ±7mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	Ð	No	ns
			Limit

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.5 V*		2.0	1.7	1.7	l.7	V
	Voltage	|Iout| v 20 μA		3.0	2.5	2.5	2.5
				4.5	3.6	3.6	3.6
				6.0	4.8	4.8	4.8
VIL	Maximum Low±Level Input	Vout = VCC ± 0.5 V*		2.0	0.3	0.3	0.3	V
	Voltage	|Iout| v 20	μA	3.0	0.5	0.5	0.5
				4.5	0.8	0.8	0.8
				6.0	1.1	1.1	1.1
VOH	Minimum High±Level Output	Vin = GND		2.0	1.8	1.8	1.8	V
	Voltage	|Iout| v 20 μA		4.5	4.0	4.0	4.0
				6.0	5.5	5.5	5.5
		Vin = GND	|Iout| v 2.4 mA	3.0	2.36	2.26	2.20
			|Iout| v 4.0 mA	4.5	3.86	3.76	3.70
			|Iout| v 5.2 mA	6.0	5.36	5.26	5.20
VOL	Maximum Low±Level Output	Vin = VCC	μA	2.0	0.2	0.2	0.2	V
	Voltage	|Iout| v 20		4.5	0.5	0.5	0.5
				6.0	0.5	0.5	0.5
		Vin = VCC	|Iout| v 2.4 mA	3.0	0.32	0.32	0.32
			|Iout| v 4.0 mA	4.5	0.32	0.37	0.40
			|Iout| v 5.2 mA	6.0	0.32	0.37	0.40

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MC74HCU04A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
							μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	1	10	40
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D). *For VCC = 2.0 V, Vout = 0.2 V or VCC ± 0.2 V.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, Input A to Output Y	2.0	70	90	105	ns
tPHL	(Figures 1 and 2)	3.0	40	45	50
		4.5	14	18	21
		6.0	12	15	18
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 2)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Inverter)*	15	pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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