MC74ACT377N
MOTOROLA MC74ACT377N, MC74ACT377MR2, MC74ACT377M, MC74ACT377MEL, MC74ACT377ML1 Datasheet
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5-1
FACT DATA
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) input loads
all flip-flops simultaneously, when the Clock Enable (CE
) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop’s Q output. The CE
input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ′ACT377 Has TTL Compatible Inputs
1920 18 17 16 15 14
21 3 4 5 6 7
V
CC
13
8
12
9
11
10
O7D7D6O6O5D5D4O4CP
CE
O0D0D1O1O2D2D3O3GND
PIN NAMES
D0–D7 Data Inputs
CE
Clock Enable (Active LOW)
Q0–Q7Data Outputs
CP Clock Pulse Input
MODE SELECT-FUNCTION TABLE
Inputs Outputs
Operating Mode
CP CE D
n
Q
n
Load ′1′ L H H
Load ′0′ L L L
H X No Change
Hold (Do Nothing)
X H X No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
OCTAL D
FLIP-FLOP WITH
CLOCK ENABLE
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
O0O1O2O3O4O5O6O
7
D0D1D2D3D4D5D6D
7
CP
CE
MC74AC377 MC74ACT377
5-2
FACT DATA
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CE
CP
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Sink/Source Current, per Pin ±50 mA
I
CC
DC VCC or GND Current per Output Pin ±50 mA
T
stg
Storage Temperature –65 to +150 °C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
′AC 2.0 5.0 6.0
VCCSupply Voltage
′ACT 4.5 5.0 5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
VCC @ 3.0 V 150
tr, t
f
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
VCC @ 4.5 V 40 ns/V
r
, t
f
′AC Devices except Schmitt Inputs
VCC @ 5.5 V 25
Input Rise and Fall Time (Note 2)
VCC @ 4.5 V 10
tr, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 5.5 V 8.0
ns/V
T
J
Junction Temperature (PDIP) 140 °C
T
A
Operating Ambient Temperature Range –40 25 85 °C
I
OH
Output Current — High –24 mA
I
OL
Output Current — Low 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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