Advance Information
8&Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
The MC74AC323/74ACT323 is an 8-bit universal shift/storage register with 3-state outputs. Its function is similar to the MC74AC299/74ACT299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load.
•Common Parallel I/O for Reduced Pin Count
•Additional Serial Inputs and Outputs for Expansion
•Four Operating Modes: Shift Left, Shift Right, Load and Store
•3-State Outputs for Bus-Oriented Applications
•Outputs Source/Sink 24 mA
•′ACT323 Has TTL Compatible Inputs
VCC |
S1 |
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DS7 |
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Q7 |
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I/O7 |
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I/O5 |
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I/O3 |
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I/O1 |
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CP |
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DS0 |
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MC74AC323
MC74ACT323
8-INPUT UNIVERSAL SHIFT/ STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
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LOGIC SYMBOL |
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S0 |
OE1 |
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OE2 |
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I/O6 |
I/O4 |
I/O2 |
I/O0 |
Q0 |
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SR |
GND |
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PIN NAMES |
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CP |
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Clock Pulse Input |
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S |
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DS0 |
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DS7 |
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DS0 |
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Serial Data Input for Right Shift |
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S1 |
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DS7 |
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Serial Data Input for Left Shift |
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Q7 |
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S |
, S |
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Mode Select Inputs |
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CP |
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0 |
1 |
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Synchronous Master Reset |
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SR |
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OE |
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OE1, OE2 |
3-State Output Enable Inputs |
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2 |
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SR |
Q0 I/O0 I/O1 |
I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 |
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I/O0±I/O7 |
Multipled Parallel Data Inputs or |
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3-State Parallel Data Outputs |
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Q0, Q7 |
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Serial Outputs |
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
FACT DATA
5-1
MC74AC323 MC74ACT323
LOGIC DIAGRAM
DS7 |
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Q7 |
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CP |
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D |
Q |
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I/O7 |
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CP |
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D |
Q |
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I/O6 |
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CP |
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D |
Q |
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I/O5 |
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CP |
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D |
Q |
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I/O4 |
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CP |
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D |
Q |
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I/O3 |
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CP |
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D |
Q |
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I/O2 |
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CP |
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D |
Q |
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I/O1 |
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CP |
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D |
Q |
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I/O0 |
S0 |
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S1 |
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OE1 |
OE2 |
DS0 |
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SR |
CP |
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Q0 |
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FACT DATA
5-2
MC74AC323 MC74ACT323
FUNCTIONAL DESCRIPTION
The MC74AC323/74ACT323 contains eight edgetriggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3 state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other
state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
TRUTH TABLE
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Inputs |
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Response |
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SR |
S1 |
S0 |
CP |
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L |
X |
X |
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Synchronous Reset; Q0 ± Q7 = LOW |
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H |
H |
H |
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Parallel Load; I/On → Qn |
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H |
L |
H |
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Shift Right; DS0 → Q0, Q0 → Q1, etc. |
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H |
H |
L |
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Shift Left; DS7 → Q7, Q7 → Q6, etc. |
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H |
L |
L |
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X |
Hold |
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H = HIGH Voltage Level |
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X = Immaterial |
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L = LOW Voltage Level |
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= LOW-to-HIGH Clock Transition |
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MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
±0.5 to +7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Iin |
DC Input Current, per Pin |
±20 |
mA |
Iout |
DC Output Sink/Source Current, per Pin |
±50 |
mA |
ICC |
DC VCC or GND Current per Output Pin |
±50 |
mA |
Tstg |
Storage Temperature |
±65 to +150 |
°C |
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Typ |
Max |
Unit |
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VCC |
Supply Voltage |
′AC |
2.0 |
5.0 |
6.0 |
V |
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′ACT |
4.5 |
5.0 |
5.5 |
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Vin, Vout |
DC Input Voltage, Output Voltage (Ref. to GND) |
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VCC |
V |
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Input Rise and Fall Time (Note 1) |
VCC @ 3.0 V |
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150 |
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tr, tf |
VCC @ 4.5 V |
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40 |
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ns/V |
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′AC Devices except Schmitt Inputs |
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VCC @ 5.5 V |
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25 |
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tr, tf |
Input Rise and Fall Time (Note 2) |
VCC @ 4.5 V |
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10 |
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ns/V |
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′ACT Devices except Schmitt Inputs |
VCC @ 5.5 V |
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8.0 |
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TJ |
Junction Temperature (PDIP) |
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140 |
°C |
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TA |
Operating Ambient Temperature Range |
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±40 |
25 |
85 |
°C |
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IOH |
Output Current Ð High |
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±24 |
mA |
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IOL |
Output Current Ð Low |
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24 |
mA |
1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA
5-3
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