Motorola MC74F168D, MC74F168N, MC74F169N, MC54F168J, MC54F169J Datasheet

4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS

The MC54/74F168 and MC54/74F169 are fully synchronous 4-stage up/ down counters. The F168 is a BCD decade counter; the F169 is a modulo-16 binary counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

•Asynchronous Counting and Loading

•Built-In Lookahead Carry Capability

•Presettable for Programmable Operation

CONNECTION DIAGRAM (TOP VIEW)

VCC				TC			Q0		Q1		Q2		Q3		CET		PE
	16		15				14		13		12		11		10		9

	1			2		3		4		5		6		7		8
						P0		P1		P2		P3
	U/D			CP										CEP	GND

MODE SELECT TABLE

					Action on Rising
	PE	CEP	CET	U/D	Clock Edge
	L	X	X	X	Load (Pn ≡	Qn)
	H	L	L	H	Count Up (Increment)
	H	L	L	L	Count Down (Decrement)
	H	H	X	X	No Change (Hold)
	H	X	H	X	No Change (Hold)
	H = HIGH Voltage Level; L = LOW Voltage Level; X = Don't Care
			STATE DIAGRAMS
						MC54/74F169
					0	1	2	3	4
	MC54/74F168
0	1	2	3		15				5
	10	15			14				6
9			4	13
	11	14			13				7
8	7	6	5	12	12	11	10	9	8
	COUNT DOWN				COUNT DOWN
	COUNT UP				COUNT UP

MC54/74F168

MC54/74F169

4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS

FAST SCHOTTKY TTL

			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1

ORDERING INFORMATION

MC54FXXXJ Ceramic

MC74FXXXN Plastic

MC74FXXXD SOIC

LOGIC SYMBOL

		9				3		4		5			6
			PE P0 P1 P2 P3
1
		U/D
7		CEP												TC			15
10		CET
2		CP
			Q0 Q1 Q2 Q3
		14				13				12			11
		VCC = Pin 16
		GND = Pin 8

FAST AND LS TTL DATA

4-82

MC54/74F168 •MC54/74F169

LOGIC DIAGRAMS

MC54/74F168
PE	P0			P1	P2	P3
CEP
CET
T	LD
		AT				TC
		AF
		ENF	LD	T
				BT
U/D				BF
UP			UP
DN			DN		DETAIL A	DETAIL A
			DETAIL A
CP	CP			ENF
			CP
		DETAIL
J	CP K			Q
Q	Q
		A
		Q
	Q0			Q1	Q2	Q3
MC54/74F169
PE	P0			P1	P2	P3
CEP
CET
T	LD
		AT				TC
		AF
		ENF	LD	T
				BT
U/D				BF
UP			UP
DN			DN		DETAIL A	DETAIL A
			DETAIL A
CP	CP			ENF
			CP
		DETAIL
J	CP K			Q
Q	Q
		A
		Q
NOTE:	Q0			Q1	Q2	Q3

These diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

FAST AND LS TTL DATA

4-83