MOTOROLA MC74HC164AF, MC74HC164AFEL, MC74HC164AFL1, MC74HC164AFL2, MC74HC164AFR1 Datasheet

MC74HC164A

8-Bit Serial-Input/

Parallel-Output Shift

Register

High±Performance Silicon±Gate CMOS

The MC74HC164A is identical in pinout to the LS164. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The MC74HC164A is an 8±bit, serial±input to parallel±output shift register. Two serial data inputs, A1 and A2, are provided so that one input may be used as a data enable. Data is entered on each rising edge of the clock. The active±low asynchronous Reset overrides the Clock and Serial Data inputs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

SERIAL	A1 1		3	QA
			4
DATA	2	DATA		QB
INPUTS	A2		5	QC
			6	QD	PARALLEL
			10	QE	DATA
					OUTPUTS
			11 QF
	CLOCK	8	12 QG
			13 QH
	RESET	9	PIN 14 = VCC

PIN 7 = GND

FUNCTION TABLE

	Inputs				Outputs
Reset	Clock	A1	A2	QA	QB	…	QH
L	X	X	X	L	L	…	L
H		X	X		No Change
H		H	D	D	QAn	…	QGn
H		D	H	D	QAn	…	QGn

D = data input

QAn ± QGn = data shifted from the preceding stage on a rising edge at the clock input.

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				MARKING
				DIAGRAMS
			14
		PDIP±14		MC74HC164AN
		N SUFFIX
				AWLYYWW
		CASE 646
			1
			14
		SOIC±14			HC164A
		D SUFFIX
				AWLYWW
	CASE 751A
			1		14
		TSSOP±14			HC
		DT SUFFIX			164A
		CASE 948G			ALYW
					1
	A		= Assembly Location
	WL or L = Wafer Lot
	YY or Y		= Year
	WW or W = Work Week
	PIN ASSIGNMENT
	A1	1	14	VCC
	A2	2	13	QH
	QA	3	12	QG
	QB	4	11	QF
	QC	5	10	QE
	QD	6	9	RESET
	GND	7	8	CLOCK
	ORDERING INFORMATION
	Device		Package		Shipping
	MC74HC164AN		PDIP±14		2000 / Box
	MC74HC164AD		SOIC±14		55 / Rail
	MC74HC164ADR2		SOIC±14		2500 / Reel
	MC74HC164ADT		TSSOP±14		96 / Rail
	MC74HC164ADTR2		TSSOP±14		2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 1		MC74HC164A/D

MC74HC164A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				±55_C to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	2.48	2.34	2.20
		|Iout| v 4.0 mA	4.5	3.98	3.84	3.70
		|Iout| v 5.2 mA	6.0	5.48	5.34	5.20

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MC74HC164A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	±55_C to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	0.26	0.33	0.40
		|Iout| v 4.0 mA	4.5	0.26	0.33	0.40
		|Iout| v 5.2 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			±55_C to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	10	10	10	MHz
	(Figures 1 and 4)	3.0	20	20	20
		4.5	40	35	30
		6.0	50	45	40
tPLH,	Maximum Propagation Delay, Clock to Q	2.0	160	200	250	ns
tPHL	(Figures 1 and 4)	3.0	100	150	200
		4.5	32	40	48
		6.0	27	34	42
tPHL	Maximum Propagation Delay, Reset to Q	2.0	175	220	260	ns
	(Figures 2 and 4)	3.0	100	150	200
		4.5	35	44	53
		6.0	30	37	45
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 4)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*	180	pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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