Motorola MC74HCT140ASD, MC74HCT140ADT, MC74HCT140ADW, MC74HCT140AN Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Inverting Buffer/ MC74HCT240A

Line	Driver/Line		Receiver			with
LSTTL-Compatible				Inputs						N SUFFIX
High±Performance Silicon±Gate CMOS							20	PLASTIC PACKAGE
									CASE 738±03
The MC74HCT240A is identical in pinout to the LS240. This device may							1
									DW SUFFIX
be used as a level converter for interfacing TTL or NMOS outputs to							20
High±Speed CMOS inputs. The HCT240A is an octal inverting buffer line									SOIC PACKAGE
							1
driver line receiver designed to be used with 3±state memory address									CASE 751D±04
drivers, clock drivers, and other bus±oriented systems. The device has
inverting outputs and two active±low output enables.							20		SD SUFFIX
The HCT240A is the inverting version of the HCT244. See also HCT241.									SSOP PACKAGE
• Output Drive Capability: 15 LSTTL Loads							1		CASE 940C±03
• TTL NMOS±Compatible Input Levels									DT SUFFIX
• Outputs Directly Interface to CMOS, NMOS, and TTL							20
								TSSOP PACKAGE
• Operating Voltage Range: 4.5 to 5.5 V							1
									CASE 948E±02
• Low Input Current: 1 μA
• In Compliance with the Requirements Defined by JEDEC Standard							ORDERING INFORMATION
No. 7A							MC74HCTXXXAN			Plastic
• Chip Complexity: 110 FETs or 27.5 Equivalent Gates
							MC74HCTXXXADW			SOIC
							MC74HCTXXXASD			SSOP
							MC74HCTXXXADT			TSSOP
		LOGIC DIAGRAM
	A1	2		18	YA1		PIN ASSIGNMENT
		4		16			ENABLE A	1	20	VCC
	A2				YA2		A1	2	19	ENABLE B
	A3	6		14	YA3		YB4	3	18	YA1
							A2	4	17	B4
	A4	8		12	YA4		YB3	5	16	YA2
DATA INPUTS					INVERTING		A3	6	15	B3
		11		9	OUTPUTS
	B1				YB1		YB2	7	14	YA3
	B2	13		7	YB2		A4	8	13	B2
							YB1	9	12	YA4
	B3	15		5	YB3		GND	10	11	B1
	B4	17		3	YB4
							FUNCTION TABLE
		1		PIN 20 = VCC				Inputs	Outputs
OUTPUT	ENABLE A			PIN 10 = GND			Enable A,
ENABLES	ENABLE B	19
							Enable B A, B		YA, YB
							L	L		H
							L	H		L
							H	X		Z
							Z = High Impedance
							X = Don't Care
2/97
Motorola, Inc. 1997		1					REV 7

MC74HCT240A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
		SOIC Package²		500
		TSSOP or SSOP Package²		450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, SOIC, TSSOP or SSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP or SSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2	2	2	V
	Voltage	|Iout| v 20 μA	5.5	2	2	2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8	0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8	0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4	4 4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4	5.4
		Vin = VIH or VIL
		|Iout| v 6 mA	4.5	3.98	3.84	3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 6 mA	4.5	0.26	0.33	0.4
Iin	Maximum Input Leakage Current	Vin = VCC or GND	5.5	± 0.1	± 1.0	± 1.0	μA
IOZ	Maximum Three State	Output in High±Impedance State	5.5	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND

MOTOROLA	2	High±Speed CMOS Logic Data
		DL129 Ð Rev 6

MC74HCT240A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C		v 85_C		v 125_C	Unit
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4		40		160	μA
	Current (per Package)	Iout = 0 μA
ICC	Additional Quiescent Supply	Vin = 2.4 V, Any One Input		≥ ±55_C			25_C to 125_C
	Current	Vin = VCC or GND, Other Inputs
		lout = 0 μA	5.5	2.9				2.4	mA

NOTES:

1.Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

2.Total Supply Current = ICC + ΣΔICC.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		± 55 to
Symbol	Parameter	25_C		v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, A to YA or B to YB	20		25	30	ns
tPHL	(Figures 1 and 3)
tPLZ,	Maximum Propagation Delay, Output Enable to YA or YB	28		35	42	ns
tPHZ	(Figures 2 and 4)
tPZL,	Maximum Propagation Delay, Output Enable to YA or YB	25		31	38	ns
tPZH	(Figures 2 and 4)
tTLH,	Maximum Output Transition Time, Any Output	12		15	18	ns
tTHL	(Figures 1 and 3)
Cin	Maximum Input Capacitance	10		10	10	pF
Cout	Maximum Three±State Output Capacitance (Output in High±Impedance	15		15	15	pF
	State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	55	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

High±Speed CMOS Logic Data	3	MOTOROLA
DL129 Ð Rev 6