MOTOROLA MC74HCT244ADT, MC74HCT244AH, MC74HCT244AF, MC74HCT244AFEL, MC74HCT244AFL1 Datasheet

MC74HCT244A

Octal 3-State Noninverting Buffer/Line Driver/

Line Receiver with LSTTL-Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT244A is identical in pinout to the LS244. This device may be used as a level converter for interfacing TTL or NMOS outputs to High±Speed CMOS inputs. The HCT244A is an octal noninverting buffer line driver line receiver designed to be used with 3±state memory address drivers, clock drivers, and other bus±oriented systems. The device has non±inverted outputs and two active±low output enables.

The HCT244A is the noninverting version of the HCT240. See also HCT241.

•Output Drive Capability: 15 LSTTL Loads

•TTL NMOS±Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 112 FETs or 28 Equivalent Gates

LOGIC DIAGRAM

	A1	2	18	YA1
	A2	4	16	YA2
	A3	6	14	YA3
	A4	8	12	YA4
	DATA INPUTS			NONINVERTING
		11	9	OUTPUTS
	B1
				YB1
	B2	13	7	YB2
	B3	15	5	YB3
	B4	17	3	YB4

OUTPUT		ENABLE A		1		PIN 20	= VCC
				19
ENABLES		ENABLE B				PIN 10	= GND

FUNCTION TABLE

Inputs		Outputs
Enable A,
Enable B	A, B	YA, YB
L	L	L
L	H	H
H	X	Z

Z = high impedance, X = don't care

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			MARKING
		DIAGRAMS
		20
	PDIP±20	MC74HCT244AN
	N SUFFIX
			AWLYYWW
20	CASE 738
1		1
		20
	SOIC WIDE±20		HCT244A
20	DW SUFFIX
			AWLYYWW
1	CASE 751D
		1	20
	TSSOP±20		HCT
20	DT SUFFIX		244A
1	CASE 948E		ALYW
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

ENABLE A		1	20	VCC
A1		2	19	ENABLE B
YB4		3	18	YA1
A2		4	17	B4
YB3		5	16	YA2
A3		6	15	B3
YB2		7	14	YA3
A4		8	13	B2
YB1		9	12	YA4
GND		10	11	B1

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT244AN	PDIP±20	1440 / Box
MC74HCT244ADW	SOIC±WIDE	38 / Rail
MC74HCT244ADWR2	SOIC±WIDE	1000 / Reel
MC74HCT244ADT	TSSOP±20	75 / Rail
MC74HCT244ADTR2	TSSOP±20	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
May, 2000 ± Rev. 9		MC74HCT244A/D

MC74HCT244A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, SOIC, SSOP or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2	2	2	V
	Voltage	|Iout| v 20 μA	5.5	2	2	2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8	0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8	0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4	4.4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4	5.4
		Vin = VIH or VIL
		|Iout| v 6 mA	4.5	3.98	3.84	3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 6 mA	4.5	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND	5.5	± 0.1	± 1.0	± 1.0	μA
	Current
IOZ	Maximum Three±State	Output in High±Impedance State	5.5	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4	40	160	μA
	Current (per Package)	Iout = 0 μA

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MC74HCT244A

ICC	Additional Quiescent Supply	Vin = 2.4 V, Any One Input		≥	±55_C	25_C to 125_C
	Current	Vin = VCC or GND, Other Inputs
		lout = 0 μA	5.5		2.9	2.4	mA

NOTES:

1.Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

2.Total Supply Current = ICC + ΣΔICC.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		± 55 to
Symbol	Parameter	25_C		v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, A to YA or B to YB	20		25	30	ns
tPHL	(Figures 1 and 3)
tPLZ,	Maximum Propagation Delay, Output Enable to YA or YB	26		33	39	ns
tPHZ	(Figures 2 and 4)
tPZL,	Maximum Propagation Delay, Output Enable to YA or YB	22		28	33	ns
tPZH	(Figures 2 and 4)
tTLH,	Maximum Output Transition Time, Any Output	12		15	18	ns
tTHL	(Figures 1 and 3)
Cin	Maximum Input Capacitance	10		10	10	pF
Cout	Maximum Three±State Output Capacitance (Output in	15		15	15	pF
	High±Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	55	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

						3 V
	tr	tf	ENABLE	1.3 V		GND
INPUT	2.7 V	3 V	A OR B	tPZL	tPLZ
A OR B	1.3 V					HIGH
	0.3 V	GND
				1.3 V		IMPEDANCE
	tPLH	tPHL	OUTPUT Y
					10%	VOL
OUTPUT	90%			tPZH
YA OR YB	1.3 V				tPHZ	VOH
	10%				90%
			OUTPUT Y	1.3 V
	tTLH	tTHL				HIGH
						IMPEDANCE
	Figure 1.			Figure 2.

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