MOTOROLA MC74HC393AFEL, MC74HC393ADTR2, MC74HC393ADT, MC74HC393AD, MC74HC393AN Datasheet

MC74HC393A

Dual 4-Stage Binary Ripple

Counter

High±Performance Silicon±Gate CMOS

The MC74HC393A is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 4±bit binary ripple counters with parallel outputs from each counter stage. A 256 counter can be obtained by cascading the two binary counters.

Internal flip±flops are triggered by high±to±low transitions of the clock input. Reset for the counters is asynchronous and active±high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393A.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

				3, 11	Q1
				4, 10
		1, 13	BINARY		Q2
	CLOCK			5, 9
			COUNTER		Q3
				6, 8
					Q4

2, 12

RESET

PIN 14 = VCC

PIN 7 = GND

FUNCTION TABLE

Inputs

Clock	Reset	Outputs
X	H	L
H	L	No Change

LL No Change L No Change L Advance to Next State

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				MARKING
				DIAGRAMS
				14
		PDIP±14		MC74HC393AN
		N SUFFIX
				AWLYYWW
		CASE 646
				1
				14
		SOIC±14		HC393A
		D SUFFIX
				AWLYWW
	CASE 751A
				1
				14
		TSSOP±14		HC
		DT SUFFIX		393A
		CASE 948G		ALYW
				1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	PIN ASSIGNMENT
	CLOCK a	1	14	VCC
	RESET a	2	13	CLOCK b
	Q1a	3	12	RESET b
	Q2a	4	11	Q1b
	Q3a	5	10	Q2
				b
	Q4a	6	9	Q3b
	GND	7	8	Q4b

ORDERING INFORMATION

Device	Package	Shipping
MC74HC393AN	PDIP±14	2000 / Box
MC74HC393AD	SOIC±14	55 / Rail
MC74HC393ADR2	SOIC±14	2500 / Reel
MC74HC393ADT	TSSOP±14	96 / Rail
MC74HC393ADTR2	TSSOP±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 2		MC74HC393A/D

MC74HC393A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
		VCC = 3.0 V	0	600
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			6.0	1.80	1.80	1.80
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	2.48	2.34	2.20
		|Iout| v 4.0 mA	4.5	3.98	3.84	3.70
		|Iout| v 5.2 mA	6.0	5.48	5.34	5.20

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MC74HC393A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	0.26	0.33	0.40
		|Iout| v 4.0 mA	4.5	0.26	0.33	0.40
		|Iout| v 5.2 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	10	9	8	MHz
	(Figures 1 and 3)	3.0	15	14	12
		4.5	30	28	25
		6.0	50	45	40
tPLH,	Maximum Propagation Delay, Clock to Q1	2.0	70	80	90	ns
tPHL	(Figures 1 and 3)	3.0	40	45	50
		4.5	24	30	36
		6.0	20	26	31
tPLH,	Maximum Propagation Delay, Clock to Q2	2.0	100	105	180	ns
tPHL	(Figures 1 and 3)	3.0	56	70	100
		4.5	34	45	55
		6.0	20	38	48
tPLH,	Maximum Propagation Delay, Clock to Q3	2.0	130	150	180	ns
tPHL	(Figures 1 and 3)	3.0	80	105	130
		4.5	44	55	70
		6.0	37	47	58
tPLH,	Maximum Propagation Delay, Clock to Q4	2.0	160	250	300	ns
tPHL	(Figures 1 and 3)	3.0	110	185	210
		4.5	52	65	82
		6.0	44	55	65
tPHL	Maximum Propagation Delay, Reset to any Q	2.0	80	95	110	ns
	(Figures 2 and 3)	3.0	48	65	75
		4.5	30	38	50
		6.0	26	33	43
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 3)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTES:

1.For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

2.Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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