MOTOROLA MC74HC02AD, MC74HC02ADR2, MC74HC02ADT, MC74HC02ADTEL, MC74HC02AFR1 Datasheet

MC74HC02A

Quad 2-Input NOR Gate

High±Performance Silicon±Gate CMOS

The MC74HC02A is identical in pinout to the LS02. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 40 FETs or 10 Equivalent Gates

LOGIC DIAGRAM

A1	2	1
			Y1
B1	3
A2	5	4	Y2
	6
B2
	8		Y = A + B
A3		10
			Y3
	9
B3
A4	11	13
			Y4
B4	12

PIN 14 = VCC

PIN 7 = GND

PIN ASSIGNMENT

Y1	1	14	VCC
A1	2	13	Y4
B1	3	12	B4
Y2	4	11	A4
A2	5	10	Y3
B2	6	9	B3
GND	7	8	A3

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			MARKING
			DIAGRAMS
			14
		PDIP±14	MC74HC02AN
		N SUFFIX
			AWLYYWW
		CASE 646
			1
			14
		SOIC±14	HC02A
		D SUFFIX
			AWLYWW
	CASE 751A
			1
			14
		TSSOP±14	HC
		DT SUFFIX	02A
		CASE 948G	ALYW
			1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	FUNCTION TABLE
	Inputs		Output
	A	B	Y
	L	L	H
	L	H	L
	H	L	L
	H	H	L

ORDERING INFORMATION

Device	Package	Shipping
MC74HC02AN	PDIP±14	2000 / Box
MC74HC02AD	SOIC±14	55 / Rail
MC74HC02ADR2	SOIC±14	2500 / Reel
MC74HC02ADT	TSSOP±14	96 / Rail
MC74HC02ADTR2	TSSOP±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HC02A/D

MC74HC02A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v85_C	v125°C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	2.48	2.34	2.20
		|Iout| v 4.0 mA	4.5	3.98	3.84	3.7
		|Iout| v 5.2 mA	6.0	5.48	5.34	5.2

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MC74HC02A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v85_C	v125°C	Unit
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	0.26	0.33	0.4
		|Iout| v 4.0 mA	4.5	0.26	0.33	0.4
		|Iout| v 5.2 mA	6.0	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	1.0	10	40	μA
	Current (per Package)	|Iout| = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC	± 55 to
Symbol	Parameter	V	25_C	v85_C	v125_C	Unit
tPLH,	Maximum Propagation Delay, Input A or B to Output Y	2.0	75	95	110	ns
tPHL	(Figures 1 and 2)	3.0	30	40	55
		4.5	15	19	22
		6.0	13	16	19
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 2)	3.0	30	40	55
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Gate)*	22	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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