MOTOROLA MC74HC175AF, MC74HC175ADTEL, MC74HC175ADR2, MC74HC175ADT, MC74HC175AFR2 Datasheet

MC74HC175A

Quad D Flip-Flop with Common Clock and Reset

High±Performance Silicon±Gate CMOS

The MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of four D flip±flops with common Reset and Clock inputs, and separate D inputs. Reset (active±low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity 166 FETs or 41.5 Equivalent Gates

				LOGIC DIAGRAM
	CLOCK		9	2	Q0
				3
					Q0
				7
			4		Q1	INVERTING
		D0		6
					Q1	AND
			5	10
	DATA	D1			Q2	NONINVERTING
				11
					Q2	OUTPUTS
	INPUTS		12
		D2		15
					Q3
			13	14
		D3			Q3

RESET 1

PIN 16 = VCC

PIN 8 = GND

FUNCTION TABLE

	Inputs		Outputs
Reset	Clock	D	Q
				Q
L	X	X	L	H
H		H	H	L
H		L	L	H
H	L	X	No Change

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC175AN
		N SUFFIX
	16		AWLYYWW
		CASE 648
		1	1
			16
		SO±16	HC175A
		D SUFFIX
	16		AWLYWW
		CASE 751B
		1	1
			16
		TSSOP±16	HC
	16	DT SUFFIX	175A
		CASE 948F	ALYW
		1
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

RESET				1	16		VCC
Q0				2	15		Q3
				3	14
	Q0						Q3
	D0			4	13		D3
	D1			5	12		D2
				6	11
	Q1						Q2
Q1				7	10		Q2
GND				8	9		CLOCK

ORDERING INFORMATION

Device	Package	Shipping
MC74HC175AN	PDIP±16	2000 / Box
MC74HC175AD	SOIC±16	48 / Rail
MC74HC175ADR2	SOIC±16	2500 / Reel
MC74HC175ADT	TSSOP±16	96 / Rail
MC74HC175ADTR2	TSSOP±16	2500 / Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
March, 2000 ± Rev. 2		MC74HC175A/D

MC74HC175A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 3.0 V	0	600
		VCC = 4.5 V	0	500
		VCC = 6.0 V		400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4 2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			6.0	1.80	1.80	1.80
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	2.48	2.34	2.20
		|Iout| v 4.0 mA	4.5	3.98	3.84	3.70
		|Iout| v 5.2 mA	6.0	5.48	5.34	5.20

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MC74HC175A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL |Iout| v 2.4 mA	3.0	0.26	0.33	0.40
		|Iout| v 4.0 mA	4.5	0.26	0.33	0.40
		|Iout| v 5.2 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

							Guaranteed Limit
						VCC
							± 55 to
Symbol	Parameter					V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)					2.0	6	4.8	4	MHz
	(Figures 1 and 4)					3.0	10	8.0	6
						4.5	30	24	20
						6.0	35	28	24
tPLH,	Maximum Propagation Delay, Clock to Q or					2.0	150	190	225	ns
		Q
tPHL	(Figures 1 and 4)					3.0	75	90	110
						4.5	26	32	38
						6.0	22	28	33
tPHL	Maximum Propagation Delay, Reset to Q or					2.0	125	155	190	ns
			Q
	(Figures 2 and 4)					3.0	70	85	110
						4.5	22	27	34
						6.0	19	24	30
tTLH,	Maximum Output Transition Time, Any Output					2.0	75	95	110	ns
tTHL	(Figures 1 and 4)					3.0	27	32	36
						4.5	15	19	22
						6.0	13	16	19
Cin	Maximum Input Capacitance					Ð	10	10	10	pF

NOTES:
1.	For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2.	Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
			Typical @ 25°C, VCC = 5.0 V
CPD		Power Dissipation Capacitance (Per Flip±Flop)*	35		pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

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