MOTOROLA MC74HC139AN, MC74HC139AF, MC74HC139AFEL, MC74HC139AFL1, MC74HC139AFL2 Datasheet

MC74HC139A

Dual 1-of-4 Decoder/

Demultiplexer

High±Performance Silicon±Gate CMOS

The MC74HC139A is identical in pinout to the LS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 1±of±4 decoders, each of which decodes a two±bit Address to one±of±four active±low outputs. Active±low Selects are provided to facilitate the demultiplexing and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and utilizing the Select as a data input.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 100 FETs or 25 Equivalent Gates

LOGIC DIAGRAM

ADDRESS	A0a	2				4	Y0a
		3				5
INPUTS	A1						Y1a	ACTIVE±LOW
	a					6
							Y2a	OUTPUTS
						7
							Y3a
SELECTa		1						PIN 16 = VCC
								PIN 8 = GND
ADDRESS	A0b	14				12	Y0b
		13				11
INPUTS	A1b						Y1b ACTIVE±LOW
						10
							Y2b	OUTPUTS
						9
							Y3b
SELECTb		15
		FUNCTION TABLE
	Inputs				Outputs
Select		A1	A0	Y0	Y1	Y2	Y3
H		X	X	H	H	H	H
L		L	L	L	H	H	H
L		L	H	H	L	H	H
L		H	L	H	H	L	H
L		H	H	H	H	H	L

X = don't care

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC139AN
		N SUFFIX
	16		AWLYYWW
		CASE 648
	1		1
			16
		SO±16	HC139A
		D SUFFIX
	16		AWLYWW
		CASE 751B
	1
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

PIN ASSIGNMENT

SELECTa		1	16		VCC
A0a		2	15		SELECTb
A1a		3	14		A0b
Y0a		4	13		A1b
Y1a		5	12		Y0b
Y2a		6	11		Y1b
Y3a		7	10		Y2b
GND		8	9		Y3b

ORDERING INFORMATION

Device	Package	Shipping
MC74HC139AN	PDIP±16	2000 / Box
MC74HC139AD	SOIC±16	48 / Rail
MC74HC139ADR2	SOIC±16	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 7		MC74HC139A/D

MC74HC139A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to	v _	v	_
Symbol	Parameter	Test Conditions		V	_				Unit
					25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA		4.5	3.15	3.15		3.15
				6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.5	0.5		0.5	V
	Voltage	|Iout| v 20 μA		4.5	1.35	1.35		1.35
				6.0	1.8	1.8		1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9		1.9	V
	Voltage	|Iout| v 20 μA		4.5	4.4	4.4		4.4
				6.0	5.9	5.9		5.9
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	3.98	3.84		3.70
			|Iout| v 5.2 mA	6.0	5.48	5.34		5.20
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1		0.1	V
	Voltage	|Iout| v 20 μA		4.5	0.1	0.1		0.1
				6.0	0.1	0.1		0.1
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	0.26	0.33		0.40
			|Iout| v 5.2 mA	6.0	0.26	0.33		0.40
Iin	Maximum Input Leakage	Vin = VCC or GND		6.0	± 0.1	± 1.0		± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	4	40		160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HC139A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, Select to Output Y	2.0	115	145	175	ns
tPHL	(Figures 1 and 3)	4.5	23	29	35
		6.0	20	25	30
tPLH,	Maximum Propagation Delay, Input A to Output Y	2.0	115	145	175	ns
tPHL	(Figures 2 and 3)	4.5	23	29	35
		6.0	20	25	30
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 3)	4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Decoder)*	55	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

	tf	tr		VALID	VALID
	90%	VCC
					VCC
SELECT	50%		INPUT A	50%
	10%	GND			GND
	tPHL	tPLH
	90%		tPLH		tPHL
OUTPUT Y	50%
	10%		OUTPUT Y	50%
	tTHL	tTLH
	Figure 1.			Figure 2.

	TEST POINT
	OUTPUT
DEVICE
UNDER									CL*
TEST

*Includes all probe and jig capacitance

Figure 3. Test Circuit

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