MOTOROLA MC74HC03AFR1, MC74HC03AFR2, MC74HC03AN, MC74HC03AFEL, MC74HC03AFL1 Datasheet

MC74HC03A

Quad 2-Input NAND Gate with Open-Drain Outputs

High±Performance Silicon±Gate CMOS

The MC74HC03A is identical in pinout to the LS03. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC03A NAND gate has, as its outputs, a high±performance MOS N±Channel transistor. This NAND gate can, therefore, with a suitable pullup resistor, be used in wired±AND applications. Having the output characteristic curves given in this data sheet, this device can be used as an LED driver or in any other application that only requires a sinking current.

•Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor

•Outputs Directly Interface to CMOS, NMOS and TTL

•High Noise Immunity Characteristic of CMOS Devices

•Operating Voltage Range: 2 to 6V

•Low Input Current: 1μA

•In Compliance With the JEDEC Standard No. 7A Requirements

•Chip Complexity: 28 FETs or 7 Equivalent Gates

DESIGN GUIDE

Criteria		Value								Unit
Internal Gate Count*		7.0								ea
Internal Gate Propagation Delay		1.5								ns
Internal Gate Power Dissipation		5.0								μW
Speed Power Product		0.0075								pJ
* Equivalent to a two±input NAND gate
LOGIC DIAGRAM
			VCC
PIN 14 = VCC		OUTPUT
	PROTECTION
PIN 7 = GND		DIODE						3,6,8,11
* Denotes open±drain outputs
										Y*

1,4,9,12

A

B 2,5,10,13

Pinout: 14±Lead Packages (Top View)

VCC		B4		A4		Y4		B3		A3		Y3
14		13		12		11		10		9		8

1		2		3		4		5		6		7
A1		B1		Y1		A2		B2		Y2	GND

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			MARKING
			DIAGRAMS
			14
		PDIP±14	MC74HC03AN
		N SUFFIX
			AWLYYWW
		CASE 646
			1
			14
		SOIC±14	HC03A
		D SUFFIX
			AWLYWW
	CASE 751A
			1
			14
		TSSOP±14	HC
		DT SUFFIX	03A
		CASE 948G	ALYW
			1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	FUNCTION TABLE
	Inputs		Output
	A	B	Y
	L	L	Z
	L	H	Z
	H	L	Z
	H	H	L

Z = High Impedance

ORDERING INFORMATION

Device	Package	Shipping
MC74HC03AN	PDIP±14	2000 / Box
MC74HC03AD	SOIC±14	55 / Rail
MC74HC03ADR2	SOIC±14	2500 / Reel
MC74HC03ADT	TSSOP±14	96 / Rail
MC74HC03ADTR2	TSSOP±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HC03A/D

MC74HC03A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400
DC CHARACTERISTICS (Voltages Referenced to GND)
					VCC		Guaranteed Limit
Symbol	Parameter	Condition			V		°	≤ °	≤	°	Unit
							±55 to 25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1V or VCC ±0.1V			2.0		1.50	1.50		1.50	V
	Voltage	|Iout| ≤ 20μA			3.0		2.10	2.10		2.10
					4.5		3.15	3.15		3.15
					6.0		4.20	4.20		4.20
VIL	Maximum Low±Level Input	Vout = 0.1V or VCC ± 0.1V			2.0		0.50	0.50		0.50	V
	Voltage	|Iout| ≤ 20μA			3.0		0.90	0.90		0.90
					4.5		1.35	1.35		1.35
					6.0		1.80	1.80		1.80
VOL	Maximum Low±Level Output	Vout = 0.1V or VCC ± 0.1V			2.0		0.1	0.1		0.1	V
	Voltage	|Iout| ≤ 20μA			4.5		0.1	0.1		0.1
					6.0		0.1	0.1		0.1
		Vin = VIH or VIL	|Iout| ≤ 2.4mA		3.0		0.26	0.33		0.40
			|Iout| ≤ 4.0mA		4.5		0.26	0.33		0.40
			|Iout| ≤ 5.2mA		6.0		0.26	0.33		0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND			6.0		±0.1	±1.0		±1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND			6.0		1.0	10		40	μA
	Current (per Package)	Iout = 0μA
IOZ	Maximum Three±State Leakage	Output in High±Impedance State			6.0		±0.5	±5.0		±10	μA
	Current	Vin = VIL or VIH
		Vout = VCC or GND

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HC03A

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

		VCC	Guaranteed Limit
Symbol	Parameter	V	±55 to 25°C	≤85°C		≤125°C	Unit
tPLZ,	Maximum Propagation Delay, Input A or B to Output Y	2.0	120	150		180	ns
tPZL	(Figures 1 and 2)	3.0	45	60		75
		4.5	24	30		36
		6.0	20	26		31
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95		110	ns
tTHL	(Figures 1 and 2)	3.0	27	32		36
		4.5	15	19		22
		6.0	13	16		19
Cin	Maximum Input Capacitance		10	10		10	pF
Cout	Maximum Three±State Output Capacitance		10	10		10	pF
	(Output in High±Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD	Power Dissipation Capacitance (Per Buffer)*	8.0	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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