MOTOROLA MC74HCT373AFL1, MC74HCT373AH, MC74HCT373AN, MC74HCT373ADWR2, MC74HCT373ADTR2 Datasheet

MC74HCT373A

Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High±Speed CMOS inputs.

The HCT373A is identical in pinout to the LS373.

The eight latches of the HCT373A are transparent D±type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched.

The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high±impedance state. Thus, data may be latched even when the outputs are not enabled.

The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs.

•Output Drive Capability: 15 LSTTL Loads

•TTL/NMOS±Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 196 FETs or 49 Equivalent Gates

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			MARKING
		DIAGRAMS
		20
	PDIP±20	MC74HCT373AN
	N SUFFIX
			AWLYYWW
20	CASE 738
1		1
		20
	SOIC WIDE±20		HCT373A
20	DW SUFFIX
			AWLYYWW
1	CASE 751D
		1	20
	TSSOP±20		HCT
20	DT SUFFIX		373A
1	CASE 948G		ALYW
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

ENABLE A	1	20	VCC
A1	2	19	ENABLE B
YB4	3	18	YA1
A2	4	17	B4
YB3	5	16	YA2
A3	6	15	B3
YB2	7	14	YA3
A4	8	13	B2
YB1	9	12	YA4
GND	10	11	B1

ORDERING INFORMATION

		Device	Package	Shipping
		MC74HCT373AN	PDIP±20	1440 / Box
		MC74HCT373ADW	SOIC±WIDE	38 / Rail
		MC74HCT373ADWR2	SOIC±WIDE	1000 / Reel
		MC74HCT373ADT	TSSOP±20	75 / Rail
		MC74HCT373ADTR2	TSSOP±20	2500 / Reel
Semiconductor Components Industries, LLC, 2000	1		Publication Order Number:
March, 2000 ± Rev. 8			MC74HCT373A/D

MC74HCT373A

LOGIC DIAGRAM

		D0	3				2	Q0
			4				5
		D1						Q1
			7				6
		D2						Q2
DATA			8				9
		D3						Q3	NONINVERTING
INPUTS			13				12
		D4						Q4	OUTPUTS
			14				15
		D5						Q5
			17				16
		D6						Q6
			18				19
		D7
								Q7
			11
LATCH ENABLE								PIN 20 = VCC
			1					PIN 10 = GND
OUTPUT ENABLE

Design Criteria	Value	Units
Internal Gate Count*	49	ea.
Internal Gate Propagation Delay	1.5	ns
		μW
Internal Gate Power Dissipation	5.0
Speed Power Product	.0075	pJ
*Equivalent to a two±input NAND gate.

PIN ASSIGNMENT

	OUTPUT	1	20	VCC
	ENABLE
	Q0	2	19	Q7
	D0	3	18	D7
	D1	4	17	D6
	Q1	5	16	Q6
	Q2	6	15	Q5
	D2	7	14	D5
	D3	8	13	D4
	Q3	9	12	Q4
	GND	10	11	LATCH
				ENABLE

FUNCTION TABLE

	Inputs		Output
Output	Latch
Enable	Enable	D	Q
L	H	H	H
L	H	L	L
L	L	X	No Change
H	X	X	Z

X = don't care

Z = high impedance

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MC74HCT373A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, SOIC, SSOP or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2.0	2.0	2.0	V
	Voltage	|Iout| v 20 μA	5.5	2.0	2.0	2.0
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8	0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8	0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4	4.4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4	5.4
		Vin = VIH or VIL
		|Iout| v 6.0 mA	4.5	3.98	3.84	3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND	5.5	± 0.1	± 1.0	± 1.0	μA
	Current
IOZ	Maximum Three±State	Output in High±Impedance State	5.5	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA

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