MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Analog |
Multiplexers/ |
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MC54/74HC4051 |
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Demultiplexers |
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MC74HC4052 |
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High±Performance Silicon±Gate CMOS |
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MC54/74HC4053 |
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The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili- |
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con±gate CMOS technology to achieve fast propagation delays, low ON |
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resistances, and low OFF leakage currents. These analog multiplexers/ |
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demultiplexers control analog voltages that may vary across the complete |
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J SUFFIX |
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power supply range (from VCC to VEE). |
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16 |
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CERAMIC PACKAGE |
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The HC4051, HC4052 and HC4053 are identical in pinout to the |
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CASE 620±10 |
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1 |
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metal±gate MC14051B, MC14052B and MC14053B. The Channel±Select |
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inputs determine which one of the Analog Inputs/Outputs is to be connected, |
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N SUFFIX |
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by means of an analog switch, to the Common Output/Input. When the |
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PLASTIC PACKAGE |
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Enable pin is HIGH, all analog switches are turned off. |
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CASE 648±08 |
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The Channel±Select and Enable inputs are compatible with standard |
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CMOS outputs; with pullup resistors they are compatible with LSTTL |
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D SUFFIX |
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outputs. |
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16 |
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SOIC PACKAGE |
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These devices have been designed so that the ON resistance (Ron) is |
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CASE 751B±05 |
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more linear over input voltage than Ron of metal±gate CMOS analog |
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switches. |
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DW SUFFIX |
For multiplexers/demultiplexers with channel±select latches, see |
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SOIC PACKAGE |
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HC4351, HC4352 and HC4353. |
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CASE 751G±02 |
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• Fast Switching and Propagation Speeds |
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DT SUFFIX |
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• Low Crosstalk Between Switches |
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16 |
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• Diode Protection on All Inputs/Outputs |
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TSSOP PACKAGE |
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1 |
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CASE 948F±01 |
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• Analog Power Supply Range (VCC ± VEE) = 2.0 to 12.0 V |
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• Digital (Control) Power Supply Range (VCC ± GND) = 2.0 to 6.0 V |
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ORDERING INFORMATION |
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• Improved Linearity and Lower ON Resistance Than Metal±Gate |
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MC54HCXXXXJ |
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Ceramic |
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Counterparts |
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MC74HCXXXXN |
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Plastic |
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• Low Noise |
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MC74HCXXXXD |
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SOIC |
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• In Compliance With the Requirements of JEDEC Standard No. 7A |
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MC74HCXXXXDW |
SOIC Wide |
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• Chip Complexity: HC4051 Ð 184 FETs or 46 Equivalent Gates |
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MC74HCXXXXDT |
TSSOP |
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HC4052 Ð 168 FETs or 42 Equivalent Gates |
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FUNCTION TABLE ± MC54/74HC4051 |
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HC4053 Ð 156 FETs or 39 Equivalent Gates |
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LOGIC DIAGRAM |
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Control Inputs |
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MC54/74HC4051 |
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Select |
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Single±Pole, 8±Position Plus Common Off |
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Enable |
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B |
A |
ON Channels |
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X0 13 |
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L |
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X0 |
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L |
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H |
X1 |
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X1 |
14 |
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L |
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H |
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X2 |
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L |
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H |
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X3 |
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X2 15 |
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ANALOG |
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L |
H |
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X4 |
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X3 |
12 |
MULTIPLEXER/ |
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3 |
COMMON |
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L |
H |
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H |
X5 |
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INPUTS/ |
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OUTPUTS |
X4 1 |
DEMULTIPLEXER |
X |
OUTPUT/ |
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L |
H |
H |
L |
X6 |
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X5 |
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INPUT |
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L |
H |
H |
H |
X7 |
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H |
X |
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NONE |
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X6 2 |
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X7 |
4 |
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Pinout: MC54/74HC4051 (Top View) |
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X = Don't Care |
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A |
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V |
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X2 |
X1 |
X0 |
X3 |
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B |
C |
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CHANNEL |
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CC |
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B |
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14 |
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12 |
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SELECT |
9 |
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INPUTS |
C |
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6 |
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ENABLE |
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PIN 16 = VCC |
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PIN 7 = VEE |
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PIN 8 = GND |
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1 |
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X4 |
X6 |
X |
X7 |
X5 |
Enable |
VEE |
GND |
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10/95 |
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Motorola, Inc. 1995 |
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REV 7 |
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MC54/74HC4051 MC74HC4052 MC54/74HC4053
FUNCTION TABLE ± MC74HC4052
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LOGIC DIAGRAM |
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Control Inputs |
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MC74HC4052 |
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Select |
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Double±Pole, 4±Position Plus Common Off |
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Enable |
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A |
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ON Channels |
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12 |
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B |
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X0 |
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L |
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L |
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L |
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Y0 |
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X0 |
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14 |
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X1 |
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X SWITCH |
13 |
X |
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L |
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H |
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Y1 |
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X1 |
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X2 |
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L |
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H |
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Y2 |
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X2 |
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11 |
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ANALOG |
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X3 |
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COMMON |
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L |
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H |
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Y3 |
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X3 |
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H |
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X |
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X |
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NONE |
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INPUTS/OUTPUTS |
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Y0 |
1 |
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OUTPUTS/INPUTS |
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X = Don't Care |
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5 |
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3 |
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Y1 |
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Y SWITCH |
Y |
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2 |
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Y2 |
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4 |
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Y3 |
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Pinout: MC74HC4052 (Top View) |
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10 |
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CHANNEL-SELECT |
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A |
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VCC |
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X2 |
X1 |
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X |
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X0 |
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X3 |
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A |
B |
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9 |
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PIN 16 = VCC |
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INPUTS |
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B |
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PIN 7 = VEE |
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16 |
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15 |
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14 |
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13 |
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12 |
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11 |
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10 |
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9 |
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ENABLE |
6 |
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PIN 8 = GND |
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1 |
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6 |
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7 |
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8 |
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Y0 |
Y2 |
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Y |
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Y3 |
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Y1 |
Enable |
VEE |
GND |
LOGIC DIAGRAM
MC54/74HC4053
Triple Single±Pole, Double±Position Plus Common Off
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X0 |
12 |
X SWITCH |
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X1 |
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ANALOG |
Y0 |
2 |
Y SWITCH |
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1 |
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INPUTS/OUTPUTS Y1 |
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Z0 |
5 |
Z SWITCH |
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Z1 |
3 |
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A 11 |
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CHANNEL-SELECT |
B |
10 |
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INPUTS |
9 |
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C |
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ENABLE |
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14X
15Y COMMON OUTPUTS/INPUTS
4 Z
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
NOTE: This device allows independent control of each switch. Channel±Select Input A controls the X±Switch, Input B controls the Y±Switch and Input C controls the Z±Switch
FUNCTION TABLE ± MC54/74HC4053
Control Inputs |
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Select |
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Enable |
C |
B |
A |
ON Channels |
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L |
L |
L |
L |
Z0 |
Y0 |
X0 |
L |
L |
L |
H |
Z0 |
Y0 |
X1 |
L |
L |
H |
L |
Z0 |
Y1 |
X0 |
L |
L |
H |
H |
Z0 |
Y1 |
X1 |
L |
H |
L |
L |
Z1 |
Y0 |
X0 |
L |
H |
L |
H |
Z1 |
Y0 |
X1 |
L |
H |
H |
L |
Z1 |
Y1 |
X0 |
L |
H |
H |
H |
Z1 |
Y1 |
X1 |
H |
X |
X |
X |
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NONE |
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X = Don't Care
Pinout: MC54/74HC4053 (Top View)
VCC |
Y |
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X |
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X1 |
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X0 |
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A |
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B |
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C |
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16 |
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15 |
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14 |
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12 |
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11 |
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10 |
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9 |
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1 |
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4 |
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5 |
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6 |
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7 |
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8 |
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Y1 |
Y0 |
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Z1 |
|
Z |
|
Z0 |
Enable |
VEE |
GND |
MOTOROLA |
2 |
MC54/74HC4051 MC74HC4052 MC54/74HC4053
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
|
|
|
|
|
|
VCC |
Positive DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
|
|
(Referenced to VEE) |
± 0.5 to + 14.0 |
|
|
VEE |
Negative DC Supply Voltage (Referenced to GND) |
± 7.0 to + 5.0 |
V |
|
VIS |
Analog Input Voltage |
VEE ± 0.5 to |
V |
|
|
|
VCC + 0.5 |
|
|
Vin |
Digital Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
|
I |
DC Current, Into or Out of Any Pin |
± 25 |
mA |
|
|
|
|
|
|
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
|
|
SOIC Package² |
500 |
|
|
|
TSSOP Package² |
450 |
|
|
|
|
|
|
|
Tstg |
Storage Temperature Range |
± 65 to + 150 |
_C |
|
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
|
_C |
|
|
Plastic DIP, SOIC or TSSOP Package |
260 |
|
|
|
Ceramic DIP |
300 |
|
|
|
|
|
|
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
|
|
Min |
Max |
Unit |
|
|
|
|
|
|
|
VCC |
Positive DC Supply Voltage |
(Referenced to GND) |
2.0 |
6.0 |
V |
|
|
|
(Referenced to VEE) |
2.0 |
12.0 |
|
|
VEE |
Negative DC Supply Voltage, Output (Referenced to |
± 6.0 |
GND |
V |
||
|
GND) |
|
|
|
|
|
|
|
|
|
|
|
|
VIS |
Analog Input Voltage |
|
|
VEE |
VCC |
V |
Vin |
Digital Input Voltage (Referenced to GND) |
|
GND |
VCC |
V |
|
VIO* |
Static or Dynamic Voltage Across Switch |
|
|
1.2 |
V |
|
TA |
Operating Temperature Range, All Package Types |
± 55 |
+ 125 |
_C |
||
tr, tf |
Input Rise/Fall Time |
|
VCC = 2.0 V |
0 |
1000 |
ns |
|
(Channel Select or Enable Inputs) |
VCC = 4.5 V |
0 |
500 |
|
|
|
|
|
VCC = 6.0 V |
0 |
400 |
|
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
3 |
MOTOROLA |
MC54/74HC4051 MC74HC4052 MC54/74HC4053
DC CHARACTERISTICS Ð Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
|
|
|
|
VCC |
Guaranteed Limit |
|
|
||
|
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
Condition |
V |
±55 to 25°C |
≤85°C |
≤125°C |
Unit |
||
|
|
|
|
|
|
|
|
|
|
VIH |
Minimum High±Level Input Voltage, |
Ron = Per Spec |
|
2.0 |
1.50 |
1.50 |
|
1.50 |
V |
|
Channel±Select or Enable Inputs |
|
|
4.5 |
3.15 |
3.15 |
|
3.15 |
|
|
|
|
|
6.0 |
4.20 |
4.20 |
|
4.20 |
|
|
|
|
|
|
|
|
|
|
|
VIL |
Maximum Low±Level Input Voltage, |
Ron = Per Spec |
|
2.0 |
0.3 |
0.3 |
|
0.3 |
V |
|
Channel±Select or Enable Inputs |
|
|
4.5 |
0.9 |
0.9 |
|
0.9 |
|
|
|
|
|
6.0 |
1.2 |
1.2 |
|
1.2 |
|
|
|
|
|
|
|
|
|
|
|
Iin |
Maximum Input Leakage Current, |
Vin = VCC or GND, |
|
6.0 |
± 0.1 |
± 1.0 |
|
± 1.0 |
μA |
|
Channel±Select or Enable Inputs |
VEE = ± 6.0 V |
|
|
|
|
|
|
|
ICC |
Maximum Quiescent Supply |
Channel Select, Enable and |
|
|
|
|
|
μA |
|
|
Current (per Package) |
VIS = VCC or GND; |
VEE = GND |
6.0 |
2 |
20 |
|
40 |
|
|
|
VIO = 0 V |
VEE = ± 6.0 |
6.0 |
8 |
80 |
|
160 |
|
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
DC CHARACTERISTICS Ð Analog Section
|
|
|
|
|
|
|
Guaranteed Limit |
|
||
|
|
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
|
Condition |
|
VCC |
VEE |
±55 to 25°C |
≤85°C |
≤125°C |
Unit |
Ron |
Maximum ªONº Resistance |
Vin = VIL or VIH; VIS = VCC to |
4.5 |
0.0 |
190 |
240 |
280 |
Ω |
||
|
|
|
VEE; IS ≤ 2.0 mA |
|
4.5 |
± 4.5 |
120 |
150 |
170 |
|
|
|
|
(Figures 1, 2) |
|
6.0 |
± 6.0 |
100 |
125 |
140 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Vin = VIL or VIH; VIS |
= VCC or |
4.5 |
0.0 |
150 |
190 |
230 |
|
|
|
|
VEE (Endpoints); IS |
≤ 2.0 mA |
4.5 |
± 4.5 |
100 |
125 |
140 |
|
|
|
|
(Figures 1, 2) |
|
6.0 |
± 6.0 |
80 |
100 |
115 |
|
|
|
|
|
|
|
|
|
|
|
|
Ron |
Maximum Difference in ªONº |
Vin = VIL or VIH; |
|
4.5 |
0.0 |
30 |
35 |
40 |
Ω |
|
|
Resistance Between Any Two |
VIS = 1/2 (VCC ± VEE); |
4.5 |
± 4.5 |
12 |
15 |
18 |
|
||
|
Channels in the Same Package |
IS ≤ 2.0 mA |
|
6.0 |
± 6.0 |
10 |
12 |
14 |
|
|
Ioff |
Maximum Off±Channel Leakage |
Vin = VIL or VIH; |
|
|
|
|
|
|
μA |
|
|
Current, Any One Channel |
VIO = VCC ± VEE; |
|
6.0 |
± 6.0 |
0.1 |
0.5 |
1.0 |
|
|
|
|
|
Switch Off (Figure 3) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum Off±Channel |
HC4051 |
Vin = VIL or VIH; |
|
6.0 |
± 6.0 |
0.2 |
2.0 |
4.0 |
|
|
Leakage Current, |
HC4052 |
VIO = VCC ± VEE; |
|
6.0 |
± 6.0 |
0.1 |
1.0 |
2.0 |
|
|
Common Channel |
HC4053 |
Switch Off (Figure 4) |
|
6.0 |
± 6.0 |
0.1 |
1.0 |
2.0 |
|
|
|
|
|
|
|
|
|
|
|
|
Ion |
Maximum On±Channel |
HC4051 |
Vin = VIL or VIH; |
|
6.0 |
± 6.0 |
0.2 |
2.0 |
4.0 |
μA |
|
Leakage Current, |
HC4052 |
Switch±to±Switch = |
|
6.0 |
± 6.0 |
0.1 |
1.0 |
2.0 |
|
|
Channel±to±Channel |
HC4053 |
VCC ± VEE; (Figure 5) |
6.0 |
± 6.0 |
0.1 |
1.0 |
2.0 |
|
MOTOROLA |
4 |
MC54/74HC4051 MC74HC4052 MC54/74HC4053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
|
|
|
VCC |
Guaranteed Limit |
|
|
||
|
|
|
|
|
|
|
|
|
Symbol |
|
Parameter |
V |
±55 to 25°C |
≤85°C |
|
≤125°C |
Unit |
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Channel±Select to Analog Output |
2.0 |
370 |
465 |
|
550 |
ns |
|
tPHL |
(Figure 9) |
|
4.5 |
74 |
93 |
|
110 |
|
|
|
|
6.0 |
63 |
79 |
|
94 |
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Analog Input to Analog Output |
2.0 |
60 |
75 |
|
90 |
ns |
|
tPHL |
(Figure 10) |
|
4.5 |
12 |
15 |
|
18 |
|
|
|
|
6.0 |
10 |
13 |
|
15 |
|
|
|
|
|
|
|
|
|
|
tPLZ, |
Maximum Propagation Delay, Enable to Analog Output |
2.0 |
290 |
364 |
|
430 |
ns |
|
tPHZ |
(Figure 11) |
|
4.5 |
58 |
73 |
|
86 |
|
|
|
|
6.0 |
49 |
62 |
|
73 |
|
|
|
|
|
|
|
|
|
|
tPZL, |
Maximum Propagation Delay, Enable to Analog Output |
2.0 |
345 |
435 |
|
515 |
ns |
|
tPZH |
(Figure 11) |
|
4.5 |
69 |
87 |
|
103 |
|
|
|
|
6.0 |
59 |
74 |
|
87 |
|
|
|
|
|
|
|
|
|
|
Cin |
Maximum Input Capacitance, Channel±Select or Enable Inputs |
|
10 |
10 |
|
10 |
pF |
|
CI/O |
Maximum Capacitance |
Analog I/O |
|
35 |
35 |
|
35 |
pF |
|
(All Switches Off) |
Common O/I: HC4051 |
|
130 |
130 |
|
130 |
|
|
|
HC4052 |
|
80 |
80 |
|
80 |
|
|
|
HC4053 |
|
50 |
50 |
|
50 |
|
|
|
|
|
|
|
|
|
|
|
|
Feedthrough |
|
1.0 |
1.0 |
|
1.0 |
|
|
|
|
|
|
|
|
|
|
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).
|
|
|
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V |
|
CPD |
Power Dissipation Capacitance (Figure 13)* |
HC4051 |
45 |
pF |
|
|
HC4052 |
80 |
|
|
|
HC4053 |
45 |
|
|
|
|
|
|
*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
5 |
MOTOROLA |