MOTOROLA MC74HCT14AN, MC74HCT14AD, MC74HCT14AFL1, MC74HCT14AFL2, MC74HCT14AFR1 Datasheet

MC74HCT14A

Hex Schmitt-Trigger Inverter with LSTTL Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high±speed CMOS inputs.

The HCT14A is identical in pinout to the LS14.

The HCT14A is useful to ªsquare upº slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds applications in noisy environments.

•Output Drive Capability: 10 LSTTL Loads

•TTL/NMOS±Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 72 FETs or 18 Equivalent Gates

LOGIC DIAGRAM

1	2
A1	Y1
3	4
A2	Y2
5	6
A3	Y3
	Y = A
9	8
A4	Y4

PIN 14 = VCC

PIN 7 = GND

11	10
A5	Y5
13	12
A6	Y6

FUNCTION TABLE

Input	Output
A	Y
L	H
H	L

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				MARKING
				DIAGRAMS
				14
		PDIP±14		MC74HCT14AN
		N SUFFIX
				AWLYYWW
		CASE 646
				1
				14
		SOIC±14		HCT14A
		D SUFFIX
				AWLYWW
	CASE 751A
				1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	PIN ASSIGNMENT
	A1	1	14	VCC
	Y1	2	13	A6
	A2	3	12	Y6
	Y2	4	11	A5
	A3	5	10	Y5
	Y3	6	9	A4
	GND	7	8	Y4

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT14AN	PDIP±14	2000 / Box
MC74HCT14AD	SOIC±14	55 / Rail
MC74HCT14ADR2	SOIC±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 7		MC74HCT14A/D

MC74HCT14A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260	_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	Ð	*	ns

*No Limit when Vin [ 50% VCC, ICC > 1 mA.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

						Temperature Limit
				± 55 to
			VCC	25_C			v 85_C			v 125_C
Symbol	Parameter	Test Conditions	Volts	Min	Max		Min	Max		Min	Max	Unit
VT+ max	Maximum Positive±Going	Vout = 0.1 V or VCC ± 0.1 V	4.5		1.9			1.9			1.9	V
	Input Threshold Voltage	|Iout| v 20 μA	5.5		2.1			2.1			2.1
VT+ min	Minimum Positive±Going	Vout = 0.1 V or VCC ± 0.1 V	4.5	1.2			1.2			1.2		V
	Input Threshold Voltage	|Iout| v 20 μA	5.5	1.4			1.4			1.4
VT± max	Maximum Positive±Going	Vout = 0.1 V or VCC ± 0.1 V	4.5		1.2			1.2			1.2
	Input Threshold Voltage	|Iout| v 20 μA	5.5		1.4			1.4			1.4
VT± min	Minimum Positive±Going	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.5			0.5			0.5
	Input Threshold Voltage	|Iout| v 20 μA	5.5	0.6			0.6			0.6
VH max	Maximum Hysteresis	Vout = 0.1 V or VCC ± 0.1 V	4.5		1.4			1.4			1.4
	Voltage	|Iout| v 20 μA	5.5		1.5			1.5			1.5
VH min	Minimum Hysteresis	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.4			0.4			0.4
	Voltage	|Iout| v 20 μA	5.5	0.4			0.4			0 4
VOH	Minimum High±Level	Vin < VT±min	4.5	4.4			4.4			4.4		V
	Output Voltage	|Iout| v 20 μA	5.5	5.4			5.4			5.4
		Vin < VT±min	4.5	3.98			3.84			3.7
		|Iout| v 4.0 mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D). (continued)

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MC74HCT14A

DC CHARACTERISTICS (Voltages Referenced to GND) ± continued

Temperature Limit

± 55 to

VCC

25_C

v 85_C

v 125_C

Symbol

Parameter

Test Conditions

Volts

Min

Max

Min

Max

Min

Max

Unit

VOL

Maximum Low±Level

Vin ≥ VT+max

4.5

0.1

0.1

0.1

V

Output Voltage

|Iout| v 20 μA

5.5

0.1

0.1

0.1

Vin ≥ VT+max

4.5

0.26

0.33

0.4

|Iout| v 4.0 mA

Iin

Maximum Input

Vin = VCC or GND

5.5

± 0.1

± 1.0

± 1.0

μA

Leakage Current

ICC

Maximum Quiescent

Vin = VCC or GND

5.5

1.0

10

40

μA

Supply Current

Iout = 0 μA

(per package)

25_C to

≥ ± 55_C

125_C

ICC

Additional Quiescent

Vin = 2.4 V, Any One Input

5.5

2.9

2.4

mA

Supply Current

Vin = VCC or GND, Other Inputs

lout = 0 μA

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

± 55 to

25_C

v 85_C

v 125_C

Symbol

Parameter

Test Conditions

Min

Max

Min

Max

Min

Max

Unit

tPLH,

Maximum Propagation

VCC = 5.0 V ± 10%

Fig.

32

40

48

ns

tPHL

Delay, Input A to Output Y

CL = 50 pF, Input tr = tf = 6.0 ns

1 & 2

(L to H)

tTLH,

Maximum Output

VCC = 5.0 V ± 10%

Fig.

15

19

22

ns

tTHL

Transition Time.

CL = 50 pF, Input tr = tf = 6.0 ns

1 & 2

Any Output

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Inverter)*	32	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

	tf	tr	3 V	TEST POINT
	2.7 V
INPUT A
	1.3 V		GND	OUTPUT
	0.3 V	tPHL
	tPLH		DEVICE
	90%		UNDER	CL*
OUTPUT Y			TEST
	1.3 V
	10%
	tTLH	tTHL
			*Includes all probe and jig capacitance
	Figure 1. Switching Waveforms		Figure 2. Test Circuit

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