MOTOROLA MC74HC390AFR1, MC74HC390AFL1, MC74HC390ADTEL, MC74HC390ADTR2, MC74HC390AF Datasheet

MC74HC390A

Dual 4-Stage Binary Ripple Counter with 2 and 5

Sections

High±Performance Silicon±Gate CMOS

The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 4±bit counters, each composed of a divide±by±two and a divide±by±five section. The divide±by±two and divide±by±five counters have separate clock inputs, and can be cascaded to implement various combinations of 2 and/or 5 up to a 100 counter.

Flip±flops internal to the counters are triggered by high±to±low transitions of the clock input. A separate, asynchronous reset is provided for each 4±bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No 7A

•Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

	CLOCK A	1, 15	2	3, 13	QA
			COUNTER
			5	5, 11 QB
	CLOCK B	4, 12		6, 10 QC
			COUNTER	7, 9	QD
		2, 14			PIN 16 = VCC
	RESET				PIN 8 = GND

FUNCTION TABLE

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC390AN
		N SUFFIX
	16		AWLYYWW
		CASE 648
		1	1
			16
		SO±16	HC390A
		D SUFFIX
	16		AWLYWW
		CASE 751B
		1	1
			16
		TSSOP±16	HC
	16	DT SUFFIX	390A
		CASE 948F	ALYW
		1
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

CLOCK Aa		1	16		VCC
RESET a		2	15		CLOCK Ab
QAa		3	14		RESET b
CLOCK Ba		4	13		QAb
QBa		5	12		CLOCK Bb
QCa		6	11		QBb
QDa		7	10		QCb
GND		8	9		QDb

Clock					ORDERING INFORMATION
A	B	Reset	Action		Device	Package	Shipping
X	X	H	Reset		MC74HC390AN	PDIP±16	2000 / Box
			2 and 5
					MC74HC390AD	SOIC±16	48 / Rail
	X	L	Increment
					MC74HC390ADR2	SOIC±16	2500 / Reel
			2
					MC74HC390ADT	TSSOP±16	96 / Rail
X		L	Increment
			5		MC74HC390ADTR2	TSSOP±16	2500 / Reel
Semiconductor Components Industries, LLC, 2000				1		Publication Order Number:
March, 2000 ± Rev. 2						MC74HC390A/D

MC74HC390A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 3.0 V	0	600
		VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20 μA		3.0	2.1	2.1	2.1
				4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA		3.0	0.9	0.9	0.9
				4.5	1.35	1.35	1.35
				6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	2.48	2.34	2.20
			|Iout| v 4.0 mA	4.5	3.98	3.84	3.70
			|Iout| v 5.2 mA	6.0	5.48	5.34	5.20
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	0.26	0.33	0.40
			|Iout| v 4.0 mA	4.5	0.26	0.33	0.40
			|Iout| v 5.2 mA	6.0	0.26	0.33	0.40

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MC74HC390A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)

			Guaranteed Limit
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	10	9	8	MHz
	(Figures 1 and 3)	3.0	15	14	12
		4.5	30	28	25
		6.0	50	45	40
tPLH,	Maximum Propagation Delay, Clock A to QA	2.0	70	80	90	ns
tPHL	(Figures 1 and 3)	3.0	40	45	50
		4.5	24	30	36
		6.0	20	26	31
tPLH,	Maximum Propagation Delay, Clock A to QC	2.0	200	250	300	ns
tPHL	(QA connected to Clock B)	3.0	160	185	210
	(Figures 1 and 3)	4.5	58	65	70
		6.0	49	62	68
tPLH,	Maximum Propagation Delay, Clock B to QB	2.0	70	80	90	ns
tPHL	(Figures 1 and 3)	3.0	40	45	50
		4.5	26	33	39
		6.0	22	28	33
tPLH,	Maximum Propagation Delay, Clock B to QC	2.0	90	105	180	ns
tPHL	(Figures 1 and 3)	3.0	56	70	100
		4.5	37	46	56
		6.0	31	39	48
tPLH,	Maximum Propagation Delay, Clock B to QD	2.0	70	80	90	ns
tPHL	(Figures 1 and 3)	3.0	40	45	50
		4.5	26	33	39
		6.0	22	28	33
tPHL	Maximum Propagation Delay, Reset to any Q	2.0	80	95	110	ns
	(Figures 2 and 3)	3.0	48	65	75
		4.5	30	38	44
		6.0	26	33	39
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 3)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	15	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Counter)*	35	pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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