MOTOROLA MC74HC4046AFR1, MC74HC4046AFR2, MC74HC4046AFL1, MC74HC4046ADTR2, MC74HC4046AF Datasheet

MC74HC4046A

Phase-Locked Loop

High±Performance Silicon±Gate CMOS

The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC4046A phase±locked loop contains three phase comparators, a voltage±controlled oscillator (VCO) and unity gain op±amp DEMOUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self±bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 (with leading±edge sensing logic) provides digital error signals PC2OUT and PCPOUT and maintains a 0 degree phase shift between SIGIN and COMPIN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op±amp output DEMOUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op±amps to minimize standby power consumption.

Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage±to±frequency conversion and motor speed control.

•Output Drive Capability: 10 LSTTL Loads

•Low Power Consumption Characteristic of CMOS Devices

•Operating Speeds Similar to LSTTL

•Wide Operating Voltage Range: 3.0 to 6.0 V

•Low Input Current: 1.0 μA Maximum (except SIGIN and COMPIN)

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Low Quiescent Current: 80 μA Maximum (VCO disabled)

•High Noise Immunity Characteristic of CMOS Devices

•Diode Protection on all Inputs

•Chip Complexity: 279 FETs or 70 Equivalent Gates

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				MARKING
				DIAGRAMS
			16
	PDIP±16		MC74HC4046AN
	N SUFFIX
16					AWLYYWW
	CASE 648
1			1
			16
	SO±16				HC4046A
	D SUFFIX
16					AWLYWW
	CASE 751B
1
			1
					16
	TSSOP±16				HC40
16	DT SUFFIX				46A
1	CASE 948F				ALYW
					1
			16
	SOEIAJ±16			74HC4046B
	F SUFFIX
16				AWLYWW
	CASE 966
1			1
A	= Assembly Location
WL	= Wafer Lot
YY	= Year
WW = Work Week
ORDERING INFORMATION
Device		Package			Shipping
MC74HC4046AN		PDIP±16			2000 / Box
MC74HC4046AD		SOIC±16			48 / Rail
MC74HC4046ADR2		SOIC±16			2500 / Reel
MC74HC4046AF		SOIC±EIAJ			See Note
MC74HC4046AFEL		SOIC±EIAJ			NO TAG
					See Note
					NO TAG
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 7		MC74HC4046A/D

MC74HC4046A

Pin No.	Symbol	Name and Function
			PIN ASSIGNMENT
1	PCPOUT	Phase Comparator Pulse Output
2	PC1OUT	Phase Comparator 1 Output	PCPout					VCC
					1	16
3	COMP	Comparator Input
	IN
4	VCOOUT	VCO Output	PC1out		2	15		PC3out
5	INH	Inhibit Input
6	C1A	Capacitor C1 Connection A	COMPin		3	14		SIGin
7	C1B	Capacitor C1 Connection B	VCOout		4	13		PC2out
8	GND	Ground (0 V) VSS
			INH		5	12		R2
9	VCOIN	VCO Input
10	DEMOUT	Demodulator Output	C1A		6	11		R1
11	R1	Resistor R1 Connection	C1B		7	10		DEMout
12	R2	Resistor R2 Connection
13	PC2OUT	Phase Comparator 2 Output
			GND		8	9		VCOin
14	SIGIN	Signal Input
15	PC3OUT	Phase Comparator 3 Output
16	VCC	Positive Supply Voltage

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 1.5 to VCC + 1.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
		SOIC Package²		500
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP and SOIC Package²		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		3.0	6.0	V
VCC	DC Supply Voltage (Referenced to GND) NON±VCO		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Pin 5)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

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MC74HC4046A

[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to	≤ 85°C
Symbol	Parameter	Test Conditions	Volts	25_C			≤ 125°C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5		1.5	V
	Voltage DC Coupled	|Iout| ≤ 20 μA	4.5	3.15	3.15		3.15
	SIGIN, COMPIN		6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5		0.5	V
	Voltage DC Coupled	|Iout| ≤ 20 μA	4.5	1.35	1.35		1.35
	SIGIN, COMPIN		6.0	1.8	1.8		1.8
VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	1.9		1.9	V
	Output Voltage	|Iout| ≤ 20 μA	4.5	4.4	4.4		4.4
	PCPOUT, PCnOUT		6.0	5.9	5.9		5.9
		Vin = VIH or VIL
		|Iout| ≤ 4.0 mA	4.5	3.98	3.84		3.7
		|Iout| ≤ 5.2 mA	6.0	5.48	5.34		5.2

(continued)

[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS ± continued (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to	≤ 85°C
Symbol	Parameter	Test Conditions	Volts	25_C			≤ 125°C	Unit
VOL	Maximum Low±Level	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.1	0.1		0.1	V
	Output Voltage Qa±Qh	|Iout| ≤ 20 μA	4.5	0.1	0.1		0.1
	PCPOUT, PCnOUT		6.0	0.1	0.1		0.1
		Vin = VIH or VIL
		|Iout| ≤ 4.0 mA	4.5	0.26	0.33		0.4
		|Iout| ≤ 5.2 mA	6.0	0.26	0.33		0.4
Iin	Maximum Input Leakage Cur-	Vin = VCC or GND	2.0	± 3.0	± 4.0		± 5.0	μA
	rent		3.0	± 7.0	± 9.0		± 11.0
	SIGIN, COMPIN		4.5	± 18.0	± 23.0		± 27.0
			6.0	± 30.0	± 38.0		± 45.0
IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0		± 10	μA
	Leakage Current	Vin = VIH or VIL
	PC2OUT	Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40		160	μA
	Current (per Package)	|Iout| = 0 μA
	(VCO disabled)
	Pins 3, 5 and 14 at VCC
	Pin 9 at GND; Input Leakage
	at
	Pins 3 and 14 to be excluded

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

[Phase Comparator Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

		VCC	Guaranteed Limit
Symbol	Parameter	Volts	± 55 to 25_C	≤ 85°C	≤ 125°C	Unit
tPLH,	Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT	2.0	175	220	265	ns
tPHL	(Figure 1)	4.5	35	44	53
		6.0	30	37	45
tPLH,	Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT	2.0	340	425	510	ns
tPHL	(Figure 1)	4.5	68	85	102
		6.0	58	72	87

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MC74HC4046A

[Phase Comparator Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

tPLH,	Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT	2.0	270	340	405	ns
tPHL	(Figure 1)	4.5	54	68	81
		6.0	46	58	69
tPLZ,	Maximum Propagation Delay, SIGIN/COMPIN Output	2.0	200	250	300	ns
tPHZ	Disable Time to PC2OUT (Figures 2 and 3)	4.5	40	50	60
		6.0	34	43	51
tPZH,	Maximum Propagation Delay, SIGIN/COMPIN Output	2.0	230	290	345	ns
tPZL	Enable Time to PC2OUT (Figures 2 and 3)	4.5	46	58	69
		6.0	39	49	59
tTLH,	Maximum Output Transition Time	2.0	75	95	110	ns
tTHL	(Figure 1)	4.5	15	19	22
		6.0	13	16	19

[VCO Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

							Guaranteed Limit
			VCC
				± 55 to				≤ 85°C
Symbol	Parameter	Test Conditions	Volts	25_C								≤ 125°C			Unit
VIH	Minimum High±Level	Vout = 0.1 V or VCC ± 0.1 V	3.0		2.1				2.1			2.1			V
	Input Voltage	|Iout| ≤ 20 μA	4.5	3.15				3.15				3.15
	INH		6.0		4.2				4.2			4.2
VIL	Maximum Low±Level	Vout = 0.1 V or VCC ± 0.1 V	3.0	0.90					0.9			0.9			V
	Input Voltage	|Iout| ≤ 20 μA	4.5	1.35				1.35				1.35
	INH		6.0		1.8				1.8			1.8
VOH	Minimum High±Level	Vin = VIH or VIL	3.0		1.9				1.9			1.9			V
	Output Voltage	|Iout| ≤ 20 μA	4.5		4.4				4.4			4.4
	VCOOUT		6.0		5.9				5.9			5.9
		Vin = VIH or VIL
		|Iout| ≤ 4.0 mA	4.5	3.98				3.84				3.7
		|Iout| ≤ 5.2 mA	6.0	5.48				5.34				5.2
VOL	Maximum Low±Level	Vout = 0.1 V or VCC ± 0.1 V	3.0		0.1				0.1			0.1			V
	Output Voltage	|Iout| ≤ 20 μA	4.5		0.1				0.1			0.1
	VCOOUT		6.0		0.1				0.1			0.1
		Vin = VIH or VIL
		|Iout| ≤ 4.0 mA	4.5	0.26				0.33				0.4
		|Iout| ≤ 5.2 mA	6.0	0.26				0.33				0.4
Iin	Maximum Input	Vin = VCC or GND	6.0		0.1				1.0			1.0			μA
	Leakage Current
	INH, VCOIN
				Min		Max		Min		Max		Min		Max
VVCOIN	Operating Voltage Range at	INH = VIL	3.0	0.1		1.0		0.1		1.0		0.1		1.0	V
	VCOIN over the range		4.5	0.1		2.5		0.1		2.5		0.1		2.5
	specified for R1; For		6.0	0.1		4.0		0.1		4.0		0.1		4.0
	linearity see Fig. 15A,
	Parallel value of R1 and R2
	should be > 2.7 kΩ
R1	Resistor Range		3.0	3.0		300		3.0		300		3.0		300	kΩ
			4.5	3.0		300		3.0		300		3.0		300
			6.0	3.0		300		3.0		300		3.0		300
R2			3.0	3.0		300		3.0		300		3.0		300
			4.5	3.0		300		3.0		300		3.0		300
			6.0	3.0		300		3.0		300		3.0		300
C1	Capacitor Range		3.0	40		No									pF
			4.5	40		Limit
			6.0	40

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MC74HC4046A

[VCO Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

				Guaranteed Limit
		VCC	± 55 to 25_C		≤ 85°C			≤ 125°C
Symbol	Parameter	Volts	Min	Max	Min	Max		Min	Max	Unit
f/T	Frequency Stability with	3.0								%/K
	Temperature Changes	4.5
	(Figure 13A, B, C)	6.0
fo	VCO Center Frequency	3.0	3							MHz
	(Duty Factor = 50%)	4.5	11
	(Figure 14A, B, C, D)	6.0	13
fVCO	VCO Frequency Linearity	3.0		See Figures 15A, B, C						%
		4.5
		6.0
∂ VCO	Duty Factor at VCOOUT	3.0			Typical 50%					%
		4.5
		6.0

[Demodulator Section]

DC ELECTRICAL CHARACTERISTICS

					Guaranteed Limit
			VCC	± 55 to 25_C		≤ 85°C			≤ 125°C
Symbol	Parameter	Test Conditions	Volts	Min	Max	Min	Max		Min	Max	Unit
RS	Resistor Range	At RS > 300 kΩ the	3.0	50	300						kΩ
		Leakage Current can	4.5	50	300
		Influence VDEMOUT	6.0	50	300
VOFF	Offset Voltage	Vi = VVCOIN = 1/2 VCC;	3.0			See Figure 12					mV
	VCOIN to VDEMOUT	Values taken over RS	4.5
		Range.	6.0
RD	Dynamic Output	VDEMOUT = 1/2 VCC	3.0			Typical 25 Ω					Ω
	Resistance at DEMOUT		4.5
			6.0

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