MOTOROLA MC74HC4020AFR2, MC74HC4020AFL2, MC74HC4020AF, MC74HC4020ADT, MC74HC4020AD Datasheet

MC74HC4020A

14-Stage Binary Ripple

Counter

High±Performance Silicon±Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of 14 master±slave flip±flops with 12 stages brought out to pins. The output of each flip±flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active±high.

State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With JEDEC Standard No. 7A Requirements

•Chip Complexity: 398 FETs or 99.5 Equivalent Gates

LOGIC DIAGRAM

														9			Q1
														7
																	Q4
														5
																	Q5
														4
																	Q6
				10										6
Clock																	Q7
														13
																	Q8
														12
																	Q9
														14
																	Q10
														15
																	Q11
														1
																	Q12
														2
																	Q13
														3
																	Q14
				11
Reset												Pin 16 = VCC
												Pin 8 = GND
VCC		Q11				Q10			Q8			Q9		Reset					Clock			Q1
16			15			14			13			12			11					10		9

Pinout: 16±Lead Plastic Package

(Top View)

1		2		3		4		5		6		7		8
Q12		Q13		Q14		Q6		Q5		Q7		Q4	GND

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC4020AN
		N SUFFIX
	16		AWLYYWW
		CASE 648
		1	1
			16
		SO±16	HC4020A
		D SUFFIX
	16		AWLYWW
		CASE 751B
		1	1
			16
		TSSOP±16	HC40
	16	DT SUFFIX	20A
		CASE 948F	ALYW
		1
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

FUNCTION TABLE

	Clock	Reset	Output State
		L	No Charge
		L	Advance to Next State
	X	H	All Outputs Are Low

ORDERING INFORMATION

Device	Package	Shipping
MC74HC4020AN	PDIP±16	2000 / Box
MC74HC4020AD	SOIC±16	48 / Rail
MC74HC4020ADR2	SOIC±16	2500 / Reel
MC74HC4020ADT	TSSOP±16	96 / Rail
MC74HC4020ADTR2	TSSOP±16	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 2		MC74HC4020A/D

MC74HC4020A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature Range		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		Plastic DIP, SOIC or TSSOP Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol		Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)			2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)			0	VCC	V
TA	Operating Temperature Range, All Package Types			± 55	+ 125	_C
tr, tf	Input Rise/Fall Time		VCC = 2.0 V	0	1000	ns
		(Figure 1)	VCC = 3.0 V	0	600
			VCC = 4.5 V	0	500
			VCC = 6.0 V	0	400
DC CHARACTERISTICS (Voltages Referenced to GND)
						VCC		Guaranteed Limit
Symbol		Parameter	Condition			V		±55 to 25°C	≤85°C	≤125°C		Unit
VIH		Minimum High±Level Input	Vout = 0.1V or VCC ±0.1V			2.0		1.50	1.50		1.50	V
		Voltage	|Iout| ≤ 20μA			3.0		2.10	2.10		2.10
						4.5		3.15	3.15		3.15
						6.0		4.20	4.20		4.20
VIL		Maximum Low±Level Input	Vout = 0.1V or VCC ± 0.1V			2.0		0.50	0.50		0.50	V
		Voltage	|Iout| ≤ 20μA			3.0		0.90	0.90		0.90
						4.5		1.35	1.35		1.35
						6.0		1.80	1.80		1.80
VOH		Minimum High±Level Output	Vin = VIH or VIL			2.0		1.9	1.9		1.9	V
		Voltage	|Iout| ≤ 20μA			4.5		4.4	4.4		4.4
						6.0		5.9	5.9		5.9
			Vin =VIH or VIL	|Iout| ≤ 2.4mA		3.0		2.48	2.34		2.20
				|Iout| ≤ 4.0mA		4.5		3.98	3.84		3.70
				|Iout| ≤ 5.2mA		6.0		5.48	5.34		5.20
VOL		Maximum Low±Level Output	Vin = VIH or VIL			2.0		0.1	0.1		0.1	V
		Voltage	|Iout| ≤ 20μA			4.5		0.1	0.1		0.1
						6.0		0.1	0.1		0.1
			Vin = VIH or VIL	|Iout| ≤ 2.4mA		3.0		0.26	0.33		0.40
				|Iout| ≤ 4.0mA		4.5		0.26	0.33		0.40
				|Iout| ≤ 5.2mA		6.0		0.26	0.33		0.40

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MC74HC4020A

DC CHARACTERISTICS (Voltages Referenced to GND)

			VCC	Guaranteed Limit
Symbol	Parameter	Condition	V	±55 to 25°C	≤85°C	≤125°C	Unit
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	±0.1	±1.0	±1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

		VCC	Guaranteed Limit
Symbol	Parameter	V	±55 to 25°C	≤85°C		≤125°C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	10	9.0		8.0	MHz
	(Figures 1 and 4)	3.0	15	14		12
		4.5	30	28		25
		6.0	50	50		40
tPLH,	Maximum Propagation Delay, Clock to Q1*	2.0	96	106		115	ns
tPHL	(Figures 1 and 4)	3.0	63	71		88
		4.5	31	36		40
		6.0	25	30		35
tPHL	Maximum Propagation Delay, Reset to Any Q	2.0	45	52		65	ns
	(Figures 2 and 4)	3.0	30	36		40
		4.5	30	35		40
		6.0	26	32		35
tPLH,	Maximum Propagation Delay, Qn to Qn+1	2.0	69	80		90	ns
tPHL	(Figures 3 and 4)	3.0	40	45		50
		4.5	17	21		28
		6.0	14	15		22
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95		110	ns
tTHL	(Figures 1 and 4)	3.0	27	32		36
		4.5	15	19		22
		6.0	13	15		19
Cin	Maximum Input Capacitance		10	10		10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n±1)] ns		VCC = 4.5	V: tP = [30.25 + 14.6 (n±1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n±1)] ns		VCC = 6.0	V: tP = [24.4 + 12 (n±1)] ns
				Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*			38	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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