Motorola MC74HC161AN, MC74HC163AD, MC74HC161AD, MC74HC163AN, MC54HC163AJ Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Presettable

Counters

MC54/74HC161A

MC54/74HC163A

High±Performance Silicon±Gate CMOS

The MC54/74HC161A and HCI63A are identical in pinout to the LS161

and LS163. The device inputs are compatible with standard CMOS outputs;

with pullup resistors, they are compatible with LSTTL outputs.

J SUFFIX

The HC161A and HC163A are programmable 4±bit binary counters with

CERAMIC PACKAGE

asynchronous and synchronous reset, respectively.

CASE 620±10

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

N SUFFIX

• Low Input Current: 1.0 μA

PLASTIC PACKAGE

• High Noise Immunity Characteristic of CMOS Devices

CASE 648±08

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 192 FETs or 48 Equivalent Gates

D SUFFIX

SOIC PACKAGE

CASE 751B±05

LOGIC DIAGRAM

ORDERING INFORMATION

MC54HCXXXAJ

Ceramic

MC74HCXXXAN

Plastic

PRESET

BCD OR

MC74HCXXXAD

SOIC

DATA

BINARY

INPUTS

OUTPUT

PIN ASSIGNMENT

CLOCK

RIPPLE

RESET

VCC

CARRY

CLOCK

RIPPLE

OUT

CARRY OUT

RESET

LOAD

ENABLE P

COUNT

PIN 16 = VCC

ENABLE P

ENABLE T

ENABLES

ENABLE T 10

PIN 8 = GND

GND

LOAD

Count

FUNCTION TABLE

Device

Mode

Reset Mode

HC161A

Binary

Asynchronous

Inputs

Output

Clock Reset*

Load

Enable P

Enable T

HC163A

Binary

Synchronous

Reset

Load Preset Data

Count

No Count

* HC163A only. HC161A is an Asynchronous Reset Device H = high level

L = low level X = don't care

10/95

Motorola, Inc. 1995

REV 6

MC54/74HC161A MC54/74HC163A

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit

VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)	± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Current, per Pin	± 25	mA
ICC	DC Supply Current, VCC and GND Pins	± 50	mA
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
	SOIC Package²	500

Tstg	Storage Temperature	± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C
	(Plastic DIP or SOIC Package)	260
	(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C

Ceramic DIP: ± 10 mW/_C from 100_ to 125_C

SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit

VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	VCC = 2.0 V	0	1000	ns
		VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)

					Guaranteed Limit
				VCC
				VCC	± 55 to	v _	v	_
Symbol	Parameter	Test Conditions		V	_	v _	v	_	Unit
Symbol	Parameter	Test Conditions			25 C	85 C		125 C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5		1.5	V
	Voltage	\|Iout\| v 20 μA		4.5	3.15	3.15		3.15
				6.0	4.2	4.2		4.2

VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.50	0.50		0.50	V
	Voltage	\|Iout\| v 20 μA		4.5	1.35	1.35		1.35
				6.0	1.80	1.80		1.80

VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9		1.9	V
	Voltage	\|Iout\| v 20 μA		4.5	4.4	4.4		4.4
				6.0	5.9	5.9		5.9

		Vin = VIH or VIL	\|Iout\| v 4.0 mA	4.5	3.98	3.84		3.7	V
			\|Iout\| v 5.2 mA	6.0	5.48	5.34		5.2
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.10	0.10		0.10	V
	Voltage	\|Iout\| v 20 μA		4.5	0.10	0.10		0.10
				6.0	0.10	0.10		0.10

		Vin = VIH or VIL	\|Iout\| v 4.0 mA	4.5	0.26	0.33		0.40	V
			\|Iout\| v 5.2 mA	6.0	0.26	0.33		0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND		6.0	± 0.1	± 1.0		± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	4	40		160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

3±2

MC54/74HC161A MC54/74HC163A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

				Guaranteed Limit
			VCC
			VCC	± 55 to
Symbol	Parameter	Fig.	V	25_C	v 85_C	v 125_C	Unit

fmax	Maximum Clock Frequency (50% Duty Cycle)*	1, 7	2.0	6	5	4	MHz
			4.5	30	24	20
			6.0	35	28	24

tPLH	Maximum Propagation Delay, Clock to Q	1, 7	2.0	120	160	200	ns
			4.5	20	23	28
			6.0	16	20	22

tPHL		1, 7	2.0	145	185	320	ns
			4.5	22	25	30
			6.0	18	20	23

tPHL	Maximum Propagation Delay, Reset to Q (HC161A Only)	2, 7	2.0	145	185	220	ns
			4.5	20	22	25
			6.0	17	19	21

tPLH	Maximum Propagation Delay, Enable T to Ripple Carry Out	3, 7	2.0	110	150	190	ns
			4.5	16	18	20
			6.0	14	15	17

tPHL		3, 7	2.0	135	175	210	ns
			4.5	18	20	22
			6.0	15	16	20

tPLH	Maximum Propagation Delay, Clock to Ripple Carry Out	1, 7	2.0	120	160	200	ns
			4.5	22	27	30
			6.0	18	22	25

tPHL		1, 7	2.0	145	185	220	ns
			4.5	22	28	35
			6.0	20	24	28

tPHL	Maximum Propagation Delay, Reset to Ripple Carry Out	2, 7	2.0	155	190	230	ns
	(HC161A Only)		4.5	22	26	30
			6.0	18	22	25

tTLH,	Maximum Output Transition Time, Any Output	2, 7	2.0	75	95	110	ns
tTHL			4.5	15	19	22
			6.0	13	16	19

Cin	Maximum Input Capacitance	1, 7	Ð	10	10	10	pF

*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out

propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See Applications information in this data sheet.

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Gate)*	30	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

3±3

MOTOROLA

MC54/74HC161A MC54/74HC163A

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

				Guaranteed Limit
			VCC
			VCC	± 55 to
Symbol	Parameter	Fig.	V	25_C	v 85_C	v 125_C	Unit

tsu	Minimum Setup Time,	5	2.0	40	60	80	ns
	Preset Data Inputs to Clock		4.5	15	20	30
			6.0	12	18	20

tsu	Minimum Setup Time,	5	2.0	60	75	90	ns
	Load to Clock		4.5	15	20	30
			6.0	12	18	20

tsu	Minimum Setup Time,	4	2.0	60	75	90	ns
	Reset to Clock (HC163A Only)		4.5	20	25	35
			6.0	17	23	25

tsu	Minimum Setup Time,	6	2.0	80	95	110	ns
	Enable T or Enable P to Clock		4.5	20	25	35
			6.0	17	23	25

th	Minimum Hold Time,	5	2.0	3	3	3	ns
	Clock to Load or Preset Data Inputs		4.5	3	3	3
			6.0	3	3	3

th	Minimum Hold Time,	4	2.0	3	3	3	ns
	Clock to Reset (HC163A Only)		4.5	3	3	3
			6.0	3	3	3

th	Minimum Hold Time,	6	2.0	3	3	3	ns
	Clock to Enable T or Enable P		4.5	3	3	3
			6.0	3	3	3

trec	Minimum Recovery Time,	2	2.0	80	95	110	ns
	Reset Inactive to Clock (HC161A Only)		4.5	15	20	26
			6.0	12	17	23

trec	Minimum Recovery Time,	5	2.0	80	95	110	ns
	Load Inactive to Clock		4.5	15	20	26
			6.0	12	17	23

tw	Minimum Pulse Width,	1	2.0	60	75	90	ns
	Clock		4.5	12	15	18
			6.0	10	13	15

tw	Minimum Pulse Width,	2	2.0	60	75	90	ns
	Reset (HC161A Only)		4.5	12	15	18
			6.0	10	13	15

tr, tf	Maximum Input Rise and Fall Times		2.0	1000	1000	1000	ns
			4.5	500	500	500
			6.0	400	400	400

MOTOROLA

3±4

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