MOTOROLA MC74HC373ADT, MC74HC373ADTEL, MC74HC373ADTR2, MC74HC373AH, MC74HC373AFR1 Datasheet
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MC74HC373A
Octal 3-State Non-Inverting
Transparent Latch
High±Performance Silicon±Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high±impedance state. Thus, data may be latched even when the outputs are not enabled.
The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.
The HC373A is the non±inverting version of the HC533A.
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 μA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 186 FETs or 46.5 Equivalent Gates
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MARKING |
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DIAGRAMS |
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20 |
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PDIP±20 |
MC74HC373AN |
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N SUFFIX |
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AWLYYWW |
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20 |
CASE 738 |
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1 |
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1 |
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20 |
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SOIC WIDE±20 |
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HC373A |
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20 |
DW SUFFIX |
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AWLYYWW |
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CASE 751D |
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1 |
20 |
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TSSOP±20 |
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HC |
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DT SUFFIX |
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373A |
1 |
CASE 948G |
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ALYW |
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A |
= Assembly Location |
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WL |
= Wafer Lot |
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YY |
= Year |
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WW = Work Week
ORDERING INFORMATION
Device |
Package |
Shipping |
MC74HC373AN |
PDIP±20 |
1440 / Box |
MC74HC373ADW |
SOIC±WIDE |
38 / Rail |
MC74HC373ADWR2 |
SOIC±WIDE |
1000 / Reel |
MC74HC373ADT |
TSSOP±20 |
75 / Rail |
MC74HC373ADTR2 |
TSSOP±20 |
2500 / Reel |
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 8 |
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MC74HC373A/D |
MC74HC373A
LOGIC DIAGRAM
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D0 |
3 |
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2 |
Q0 |
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4 |
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5 |
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D1 |
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Q1 |
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7 |
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6 |
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D2 |
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Q2 |
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DATA |
8 |
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9 |
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D3 |
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Q3 |
NONINVERTING |
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INPUTS |
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13 |
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12 |
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D4 |
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Q4 |
OUTPUTS |
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14 |
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15 |
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D5 |
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Q5 |
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17 |
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16 |
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D6 |
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Q6 |
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18 |
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19 |
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D7 |
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Q7 |
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LATCH ENABLE |
11 |
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PIN 20 = VCC |
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1 |
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PIN 10 = GND |
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OUTPUT ENABLE |
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Design Criteria |
Value |
Units |
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Internal Gate Count* |
46.5 |
ea |
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Internal Gate Propagation Delay |
1.5 |
ns |
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Internal Gate Power Dissipation |
5.0 |
μW |
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Speed Power Product |
0.0075 |
pJ |
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*Equivalent to a two±input NAND gate. |
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PIN ASSIGNMENT
OUTPUT |
1 |
20 |
VCC |
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ENABLE |
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Q0 |
2 |
19 |
Q7 |
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D0 |
3 |
18 |
D7 |
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D1 |
4 |
17 |
D6 |
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Q1 |
5 |
16 |
Q6 |
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Q2 |
6 |
15 |
Q5 |
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D2 |
7 |
14 |
D5 |
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D3 |
8 |
13 |
D4 |
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Q3 |
9 |
12 |
Q4 |
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GND |
10 |
11 |
LATCH |
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ENABLE |
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FUNCTION TABLE
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Inputs |
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Output |
Output |
Latch |
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Enable |
Enable |
D |
Q |
L |
H |
H |
H |
L |
H |
L |
L |
L |
L |
X |
No Change |
H |
X |
X |
Z |
X = Don't Care
Z = High Impedance
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MC74HC373A
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
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Vin |
DC Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Iin |
DC Input Current, per Pin |
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± 20 |
mA |
Iout |
DC Output Current, per Pin |
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± 35 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
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PD |
Power Dissipation in Still Air, |
Plastic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
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± 65 to + 150 |
_C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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(Plastic DIP, SOIC, SSOP or TSSOP Package) |
260 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C
TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
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2.0 |
6.0 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
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TA |
Operating Temperature, All Package Types |
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± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
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(Figure 1) |
VCC = 4.5 V |
0 |
500 |
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VCC = 6.0 V |
0 |
400 |
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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VIH |
Minimum High±Level Input |
Vout = VCC ± 0.1 V |
2.0 |
1.5 |
1.5 |
1.5 |
V |
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Voltage |
|Iout| v 20 |
μA |
3.0 |
2.1 |
2.1 |
2.1 |
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4.5 |
3.15 |
3.15 |
3.15 |
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6.0 |
4.2 |
4.2 |
4.2 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V |
2.0 |
0.5 |
0.5 |
0.5 |
V |
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Voltage |
|Iout| v 20 μA |
3.0 |
0.9 |
0.9 |
0.9 |
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4.5 |
1.35 |
1.35 |
1.35 |
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6.0 |
1.8 |
1.8 |
1.8 |
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VOH |
Minimum High±Level Output |
Vin = VIH |
μA |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
4.4 |
4.4 |
4.4 |
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6.0 |
5.9 |
5.9 |
5.9 |
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Vin = VIH |
|Iout| v 2.4 mA |
3.0 |
2.48 |
2.34 |
2.2 |
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|Iout| v 6.0 mA |
4.5 |
3.98 |
3.84 |
3.7 |
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|Iout| v 7.8 mA |
6.0 |
5.48 |
5.34 |
5.2 |
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VOL |
Maximum Low±Level Output |
Vin = VIL |
μA |
2.0 |
0.1 |
0.1 |
0.1 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
0.1 |
0.1 |
0.1 |
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6.0 |
0.1 |
0.1 |
0.1 |
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Vin = VIL |
|Iout| v 2.4 mA |
3.0 |
0.26 |
0.33 |
0.4 |
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|Iout| v 6.0 mA |
4.5 |
0.26 |
0.33 |
0.4 |
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|Iout| v 7.8 mA |
6.0 |
0.26 |
0.33 |
0.4 |
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