Motorola MC74F648DW, MC74F648N, MC74F646DW, MC54F646J, MC54F648J Datasheet

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OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS

These devices consist of bus transceiver circuits with 3-state D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable OE is Active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register.

•Independent Registers for A and B

•Multiplexed Real-Time and Stored Data

•Choice of True (F646) and Inverting (F648) Data Paths

•3-State Outputs

PIN ASSIGNMENTS

	VCC CPBA SBA							OE			B0		B1		B2		B3		B4		B5		B6		B7
	24		23		22		21				20		19		18		17		16		15		14		13

F646

	1		2		3		4				5				6				7				8				9				10				11				12
CPAB SAB					DIR			A0			A1				A2					A3				A4				A5				A6				A7			GND
	VCC CPBA				SBA																								4				5				6				7
								OE				B	0			B	1			B	2			B	3			B				B				B				B
	24		23		22		21				20				19				18				17				16				15				14				13

F648

	1		2		3		4				5				6				7				8				9				10				11				12
CPAB SAB					DIR				0				1				2				3				4				5				6				7		GND
								A				A				A				A				A				A				A				A

		4		5		6		7		8		9		10		11		LOGIC SYMBOLS
1		CPAB A0		A1		A2		A3		A4		A5		A6		A7		1
2		SAB																2
3		DIR							F646									3
23		CPBA																23
22		SBA																22
21		OE B0 B1				B2		B3 B4				B5 B6				B7		21
		20		19		18		17		16		15		14		13

MC54/74F646

MC54/74F648

OCTAL TRANSCEIVER/REGISTER

WITH 3-STATE OUTPUTS

FAST SCHOTTKY TTL

	24	J SUFFIX
	1
		CERAMIC

CASE 758-01

24		N SUFFIX
		PLASTIC
	1
		CASE 724-03

24	DW SUFFIX
	SOIC
1	CASE 751E-03

ORDERING INFORMATION

MC54FXXXJ Ceramic

MC74FXXXN Plastic

MC74FXXXDW SOIC

4

5

6

7

8

9

10

11

CPAB A0

A1

A2

A3

A4

A5

A6

A7

SAB

DIR

F648

CPBA

SBA

OE B0 B1

B2

B3

B4

B5

B6

B7

20 19 18 17 16 15 14 13

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

FAST AND LS TTL DATA

4-241

MC54/74F646 •MC54/74F648

FUNCTION TABLE

			Inputs				Data I/O*		Operation/Function
	OE bar	DIR	CPAB	CPBA	SAB	SBA	A0±A7	B0±B7
	H	X	H or L	H or L	X	X	Input	Input	Isolation
	H	X	↑	X	X	X	Input	Input	Store An Data in A Register
	H	X	X	↑	X	X	Input	Input	Store Bn Data in B Register
	H	X	↑	↑	X	X	Input	Input	Store An/Bn Data in A/B Register
	L	H	X	X	L	X	Input	Output	An to Bn Ð Real Time (Transparent Mode)
	L	H	↑	X	L	X	Input	Output	Store An Data in A Register
	L	H	H or L	X	H	X	Input	Output	A Register to Bn (Stored Mode)
	L	H	↑	X	H	X	Input	Output	Clock An Data to Bn and into A Register
	L	L	X	X	X	L	Output	Input	Bn to An Ð Real Time (Transparent Mode)
	L	L	X	↑	X	L	Output	Input	Store Bn Data in B Register
	L	L	X	H or L	X	H	Output	Input	B Register to An (Stored Mode)
	L	L	X	↑	X	H	Output	Input	Clock An Data to Bn and into B Register

*The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs. Data input functions are always enabled; i.e., data at the *bus pins will be stored on every low-to-high transition of the appropriate clock inputs.

H = HIGH voltage level L = LOW voltage level X = Don't Care

↑ = Low-to-High transition

GUARANTEED OPERATING RANGES

	Symbol	Parameter			Min	Typ	Max	Unit
	VCC	DC Supply Voltage		54, 74	4.5	5.0	5.5	V
	TA	Operating Ambient Temperature Range		54	±55	25	125	°C
				74	0	25	70
	IOH	Output Current	High	54	Ð	Ð	±12	mA
				74	Ð	Ð	±15
	IOL	Output Current	Low	54	Ð	Ð	48	mA
				74	Ð	Ð	64

FAST AND LS TTL DATA

4-242