MOTOROLA MC74HC157ADT, MC74HC157ADTR2, MC74HC157AF, MC74HC157AFEL, MC74HC157AFL1 Datasheet

MC74HC157A

Quad 2-Input Data

Selectors / Multiplexers

High±Performance Silicon±Gate CMOS

The MC74HC157A is identical in pinout to the LS157. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninverted form. A high level on the Output Enable input sets all four Y outputs to a low level.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 82 FETs or 20.5 Equivalent Gates

LOGIC DIAGRAM

	A0	2
		5
NIBBLE	A1
		11
A INPUTS	A2			4
					Y0
		14
	A3			7
					Y1
				9		DATA
		3			Y2 OUTPUTS
	B0			12
					Y3
		6
NIBBLE	B1
		10
B INPUTS	B2
		13
	B3					PIN 16 = VCC
						PIN 8 = GND
SELECT		1
OUTPUT		15
	ENABLE
		FUNCTION TABLE
		Inputs
		Output		Outputs
		Enable	Select	Y0 ± Y3
		H	X	L
		L	L	A0 ± A3
		L	H	B0 ± B3

X = don't care

A0 ± A3, B0 ± B3 = the levels of the respective Data±Word Inputs.

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				MARKING
				DIAGRAMS
				16
		PDIP±16		MC74HC157AN
		N SUFFIX
	16			AWLYYWW
		CASE 648
	1			1
				16
		SO±16		HC157A
		D SUFFIX
	16			AWLYWW
		CASE 751B
	1
				1
				16
		TSSOP±16		HC
	16	DT SUFFIX		157A
	1	CASE 948F		ALYW
				1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year
	WW = Work Week
	PIN ASSIGNMENT
	SELECT	1	16	VCC
	A0	2	15	OUTPUT
				ENABLE
	B0	3	14	A3
	Y0	4	13	B3
	A1	5	12	Y3
	B1	6	11	A2
	Y1	7	10	B2
	GND	8	9	Y2

ORDERING INFORMATION

Device	Package	Shipping
MC74HC157AN	PDIP±16	2000 / Box
MC74HC157AD	SOIC±16	48 / Rail
MC74HC157ADR2	SOIC±16	2500 / Reel
MC74HC157ADT	TSSOP±16	96 / Rail
MC74HC157ADTR2	TSSOP±16	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HC157A/D

MC74HC157A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage		0	VCC	V
	(Referenced to GND)
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20	μA	3.0	2.1	2.1	2.1
				4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V		2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA		3.0	0.9	0.9	0.9
				4.5	1.35	1.35	1.35
				6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH	μA	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vin = VIH	|Iout| v 2.4 mA	3.0	2.48	2.34	2.2
			|Iout| v 6.0 mA	4.5	3.98	3.84	3.7
			|Iout| v 7.8 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin = VIL	μA	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin = VIL	|Iout| v 2.4 mA	3.0	0.26	0.33	0.4
			|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
			|Iout| v 7.8 mA	6.0	0.26	0.33	0.4

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MC74HC157A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, Input A or B to Output Y	2.0	105	130	160	ns
tPHL	(Figures 1 and 4)	3.0	65	85	115
		4.5	21	26	32
		6.0	18	22	27
tPLH,	Maximum Propagation Delay, Select to Output Y	2.0	110	140	165	ns
tPHL	(Figures 2 and 4)	3.0	70	90	115
		4.5	22	28	33
		6.0	19	24	28
tPLH,	Maximum Propagation Delay, Output Enable to Output Y	2.0	100	125	150	ns
tPHL	(Figures 3 and 4)	3.0	60	80	110
		4.5	20	25	30
		6.0	17	21	26
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 4)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*	33	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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