MOTOROLA MC74HCT541AN, MC74HCT541AFL1, MC74HCT541ADWR2, MC74HCT541AF, MC74HCT541AFEL Datasheet

MC74HCT541A

Octal 3-State Non-Inverting

Buffer/Line Driver/

Line Receiver With

LSTTL-Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT541A is identical in pinout to the LS541. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs.

The HCT541A is an octal non±inverting buffer/line driver/line receiver designed to be used with 3±state memory address drivers, clock drivers, and other bus±oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active±low output enables.

•Output Drive Capability: 15 LSTTL Loads

•TTL/NMOS±Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5V

•Low Input Current: 1μA

•In Compliance With the JEDEC Standard No. 7A Requirements

•Chip Complexity: 134 FETs or 33.5 Equivalent Gates

LOGIC DIAGRAM

	A1	2	18	Y1
	A2	3	17	Y2
	A3	4	16	Y3
	A4	5	15	Y4
Data					Non±Inverting
Inputs		6	14		Outputs
	A5			Y5
	A6	7	13	Y6
	A7	8	12	Y7
	A8	9	11	Y8	VCC
Output	OE1	1	PIN 20 = VCC		20
Enables	OE2	19
			PIN 10 = GND

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			MARKING
			DIAGRAMS
			20
		PDIP±20	MC74HCT541AN
		N SUFFIX
			AWLYYWW
	20	CASE 738
	1		1
			20
	SOIC WIDE±20		HCT541A
	20	DW SUFFIX
			AWLYYWW
	1	CASE 751D
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT541AN	PDIP±20	1440 / Box
MC74HCT541ADW	SOIC±WIDE	38 / Rail
MC74HCT541ADWR2	SOIC±WIDE	1000 / Reel

		FUNCTION TABLE
		Inputs			Output Y
	OE1	OE2	A
	L	L	L		L
	L	L	H		H
	H	X	X		Z
	X	H	X		Z
	Z = High Impedance
	X = Don't Care
Pinout: 20±Lead Packages (Top View)
OE2	Y1	Y2	Y3	Y4	Y5	Y6	Y7	Y8
19	18	17	16	15	14	13	12	11

		1		2		3		4		5		6		7		8		9		10
		OE1		A1		A2		A3		A4		A5		A6		A7		A8	GND
Semiconductor Components Industries, LLC, 2000	1												Publication Order Number:
March, 2000 ± Rev. 2																MC74HCT541A/D

MC74HCT541A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 35	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature Range		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	Plastic DIP or SOIC Package		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

VCC

DC Supply Voltage (Referenced to GND)

4.5

5.5

V

Vin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

0

VCC

V

TA

Operating Temperature Range, All Package Types

± 55

+ 125

_C

tr, tf

Input Rise/Fall Time (Figure 1)

0

500

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

Guaranteed Limit

Symbol

Parameter

Condition

V

±55 to 25°C

≤85°C

≤125°C

Unit

VIH

Minimum High±Level Input

Vout = 0.1V or VCC ± 0.1V

4.5

2.0

2.0

2.0

V

Voltage

|Iout| ≤ 20μA

5.5

2.0

2.0

2.0

VIL

Maximum Low±Level Input

Vout = 0.1V or VCC ± 0.1V

4.5

0.8

0.8

0.8

V

Voltage

|Iout| ≤ 20μA

5.5

0.8

0.8

0.8

VOH

Minimum High±Level Output

Vin = VIH or VIL

4.5

4.4

4.4

4.4

V

Voltage

|Iout| ≤ 20μA

5.5

5.4

5.4

5.4

Vin = VIH or VIL

|Iout| ≤ 6.0mA

4.5

3.98

3.84

3.70

VOL

Maximum Low±Level Output

Vin = VIH or VIL

4.5

0.1

0.1

0.1

V

Voltage

|Iout| ≤ 20μA

5.5

0.1

0.1

0.1

Vin = VIH or VIL

|Iout| ≤ 6.0mA

4.5

0.26

0.33

0.40

Iin

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

μA

IOZ

Maximum Three±State Leakage

Output in High Impedance State

5.5

±0.5

±5.0

±10.0

μA

Current

Vin = VIL or VIH

Vout = VCC or GND

ICC

Maximum Quiescent Supply

Vin = VCC or GND

5.5

4

40

160

μA

Current (per Package)

Iout = 0μA

ICC

Additional Quiescent Supply

V = 2.4V, Any One Input

≥

°

°

Current

in

±55 C

25 to 125 C

Vin = VCC or GND, Other Inputs

Iout = 0μA

5.5

2.9

2.4

mA

1.Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

2.Total Supply Current = ICC + ΣΔICC.

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MC74HCT541A

AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)

		Guaranteed Limit
Symbol	Parameter	±55 to 25°C	≤85°C		≤125°C	Unit
tPLH,	Maximum Propagation Delay, Input A to Output Y	23	28		32	ns
tPHL	(Figures 1 and 3)
tPLZ,	Maximum Propagation Delay, Output Enable to Output Y	30	34		38	ns
tPHZ	(Figures 2 and 4)
tPZL,	Maximum Propagation Delay, Output Enable to Output Y	30	34		38	ns
tPZH	(Figures 2 and 4)
tTLH,	Maximum Output Transition Time, Any Output	12	15		18	ns
tTHL	(Figures 1 and 3)
Cin	Maximum Input Capacitance	10	10		10	pF
Cout	Maximum Three±State Output Capacitance (Output in High Impedance	15	15		15	pF
	State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Buffer)*	55	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

t		tf				3.0V
r			OE1 or OE2	1.3V	1.3V
	90%		3.0V			GND
INPUT A	1.3V			tPZL	tPLZ
						HIGH
	10%		GND
						IMPEDANCE
tPLH		tPHL	OUTPUT Y	1.3V
		90%			10%	VOL
				tPZH tPHZ
OUTPUT Y	1.3V
	10%
			OUTPUT Y		90%	VOH
				1.3V
t	TLH	tTHL
						HIGH
						IMPEDANCE
		Figure 1.		Figure 2.

TEST CIRCUITS

TEST

TEST

POINT

POINT

OUTPUT

OUTPUT

1kΩ

DEVICE

DEVICE

UNDER

CL*

UNDER

CL*

TEST

TEST

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL. CONNECT TO GND WHEN

TESTING tPHZ and tPZH.

*Includes all probe and jig capacitance	*Includes all probe and jig capacitance
Figure 3.	Figure 4.

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