MOTOROLA MC74HC161AFR2, MC74HC161AN, MC74HC161AFR1, MC74HC163AD, MC74HC163ADR2 Datasheet

MC74HC161A,

MC74HC163A

Presettable Counters

High±Performance Silicon±Gate CMOS

The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC161A and HC163A are programmable 4±bit binary counters with asynchronous and synchronous reset, respectively.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 192 FETs or 48 Equivalent Gates

Count

Device

Mode

Reset Mode

HC161A

Binary

Asynchronous

HC163A

Binary

Synchronous

LOGIC DIAGRAM

P0

3

14

Q0

PRESET

P1

4

13

Q1

BCD OR

DATA

P2

5

12

BINARY

INPUTS

Q2

OUTPUT

P3

6

11

Q3

2

15

RIPPLE

CLOCK

CARRY

OUT

RESET

1

LOAD

9

PIN 16 = VCC

PIN 8 = GND

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC16xAN
		N SUFFIX
	16		AWLYYWW
		CASE 648
	1		1
			16
		SO±16	HC16xA
		D SUFFIX
	16		AWLYWW
		CASE 751B
	1
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

ORDERING INFORMATION

Device					Package	Shipping
MC74HC16xAN					PDIP±16	2000 / Box
MC74HC16xAD					SOIC±16	48 / Rail
MC74HC16xADR2					SOIC±16	2500 / Reel
PIN ASSIGNMENT
RESET		1	16		VCC
CLOCK		2	15		RIPPLE
					CARRY OUT
P0		3	14		Q0
		4	13
P1					Q1
P2		5	12		Q2
P3		6	11		Q3
ENABLE P		7	10		ENABLE T
GND		8	9		LOAD

COUNT		ENABLE P	7	FUNCTION TABLE
				Inputs			Output
ENABLES		ENABLE T	10
			Clock Reset*	Load	Enable P	Enable T	Q
			L	X	X	X	Reset
			H	L	X	X	Load Preset Data
			H	H	H	H	Count
			H	H	L	X	No Count
			H	H	X	L	No Count

*HC163A only. HC161A is an Asynchronous Reset Device H = high level, L = low level, X = don't care

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HC161A/D

MC74HC161A, MC74HC163A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	VCC = 2.0 V	0	1000	ns
		VCC = 3.0 V	0	600
		VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

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MC74HC161A, MC74HC163A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

									Guaranteed Limit
								VCC
									± 55 to	v _	v	_
Symbol	Parameter			Test Conditions				V	_				Unit
									25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V						2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA						3.0	2.1	2.1		2.1
								4.5	3.15	3.15		3.15
								6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V						2.0	0.5	0.5		0.5	V
	Voltage	|Iout| v 20 μA						3.0	0.9	0.9		0.9
								4.5	1.35	1.35		1.35
								6.0	1.8	1.8		1.8
VOH	Minimum High±Level Output	V	= V	IH	or V	IL		2.0	1.9	1.9		1.9	V
		in
	Voltage	|Iout| v 20 μA						4.5	4.4	4.4		4.4
								6.0	5.9	5.9		5.9
		Vin = VIH or VIL					|Iout| v 3.6 mA	3.0	2.48	2.34		2.2
							|Iout| v 4.0 mA	4.5	3.98	3.84		3.7
							|Iout| v 5.2 mA	6.0	5.48	5.34		5.2
VOL	Maximum Low±Level Output	V	= V	IH	or V	IL		2.0	0.1	0.1		0.1	V
		in
	Voltage	|Iout| v 20 μA						4.5	0.1	0.1		0.1
								6.0	0.1	0.1		0.1
		Vin = VIH or VIL					|Iout| v 3.6 mA	3.0	0.26	0.33		0.4
							|Iout| v 4.0 mA	4.5	0.26	0.33		0.4
							|Iout| v 5.2 mA	6.0	0.26	0.33		0.4
Iin	Maximum Input Leakage	Vin = VCC or GND						6.0	± 0.1	± 1.0		± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND						6.0	4.0	40		160	μA
	Current (per Package)			μ
		Iout = 0 A

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HC161A, MC74HC163A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Fig.	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)*	1, 7	2.0	6	5	4	MHz
			3.0	15	12	10
			4.5	30	24	20
			6.0	35	28	24
tPLH	Maximum Propagation Delay, Clock to Q	1, 7	2.0	120	160	200	ns
			3.0	75	120	150
			4.5	20	23	28
			6.0	16	20	22
tPHL		1, 7	2.0	145	185	220	ns
			3.0	100	135	150
			4.5	22	25	30
			6.0	18	20	23
tPHL	Maximum Propagation Delay, Reset to Q (HC161A Only)	2, 7	2.0	145	185	220	ns
			3.0	100	135	150
			4.5	20	22	25
			6.0	17	19	21
tPLH	Maximum Propagation Delay, Enable T to Ripple Carry Out	3, 7	2.0	110	150	190	ns
			3.0	60	115	140
			4.5	16	18	20
			6.0	14	15	17
tPHL		3, 7	2.0	135	175	210	ns
			3.0	100	130	160
			4.5	18	20	22
			6.0	15	16	20
tPLH	Maximum Propagation Delay, Clock to Ripple Carry Out	1, 7	2.0	120	160	200	ns
			3.0	75	135	150
			4.5	22	27	30
			6.0	18	22	25
tPHL		1, 7	2.0	145	185	220	ns
			3.0	100	135	150
			4.5	22	28	35
			6.0	20	24	28
tPHL	Maximum Propagation Delay, Reset to Ripple Carry Out	2, 7	2.0	155	190	230	ns
	(HC161A Only)		3.0	120	140	155
			4.5	22	26	30
			6.0	18	22	25
tTLH,	Maximum Output Transition Time, Any Output	2, 7	2.0	75	95	110	ns
tTHL			3.0	30	40	55
			4.5	15	19	22
			6.0	13	16	19
Cin	Maximum Input Capacitance	1, 7	Ð	10	10	10	pF

*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See Applications information in this data sheet.

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Gate)*	45	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HC161A, MC74HC163A

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

					Guaranteed Limit
				VCC
					± 55 to
	Symbol	Parameter	Fig.	V	25_C	v 85_C	v 125_C	Unit
	tsu	Minimum Setup Time,	5	2.0	40	60	80	ns
		Preset Data Inputs to Clock		3.0	20	30	40
				4.5	15	20	30
				6.0	12	18	20
	tsu	Minimum Setup Time,	5	2.0	60	75	90	ns
		Load to Clock		3.0	25	30	40
				4.5	15	20	30
				6.0	12	18	20
	tsu	Minimum Setup Time,	4	2.0	60	75	90	ns
		Reset to Clock (HC163A Only)		3.0	25	30	40
				4.5	20	25	35
				6.0	17	23	25
	tsu	Minimum Setup Time,	6	2.0	80	95	110	ns
		Enable T or Enable P to Clock		3.0	35	40	50
				4.5	20	25	35
				6.0	17	23	25
	th	Minimum Hold Time,	5	2.0	3	3	3	ns
		Clock to Load or Preset Data Inputs		3.0	3	3	3
				4.5	3	3	3
				6.0	3	3	3
	th	Minimum Hold Time,	4	2.0	3	3	3	ns
		Clock to Reset (HC163A Only)		3.0	3	3	3
				4.5	3	3	3
				6.0	3	3	3
	th	Minimum Hold Time,	6	2.0	3	3	3	ns
		Clock to Enable T or Enable P		3.0	3	3	3
				4.5	3	3	3
				6.0	3	3	3
	trec	Minimum Recovery Time,	2	2.0	80	95	110	ns
		Reset Inactive to Clock (HC161A Only)		3.0	35	40	50
				4.5	15	20	26
				6.0	12	17	23
	trec	Minimum Recovery Time,	5	2.0	80	95	110	ns
		Load Inactive to Clock		3.0	35	40	50
				4.5	15	20	26
				6.0	12	17	23
	tw	Minimum Pulse Width,	1	2.0	60	75	90	ns
		Clock		3.0	25	30	40
				4.5	12	15	18
				6.0	10	13	15
	tw	Minimum Pulse Width,	2	2.0	60	75	90	ns
		Reset (HC161A Only)		3.0	25	30	40
				4.5	12	15	18
				6.0	10	13	15
	tr, tf	Maximum Input Rise and Fall Times		2.0	1000	1000	1000	ns
				3.0	800	800	800
				4.5	500	500	500
				6.0	400	400	400

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