MOTOROLA MC74HC573ADW, MC74HC573AF, MC74HC573AFEL, MC74HC573ADTEL, MC74HC573ADT Datasheet

MC74HC573A

Octal 3-State Noninverting

Transparent Latch

High±Performance Silicon±Gate CMOS

The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 218 FETs or 54.5 Equivalent Gates

http://onsemi.com

			MARKING
		DIAGRAMS
		20
	PDIP±20	MC74HC573AN
	N SUFFIX
			AWLYYWW
20	CASE 738
1		1
		20
SOIC WIDE±20			HC573A
20	DW SUFFIX
			AWLYYWW
1	CASE 751D
		1	20
	TSSOP±20		HC
20	DT SUFFIX		573A
1	CASE 948E		ALYW
			1
A	= Assembly Location
WL	= Wafer Lot
YY	= Year

WW = Work Week

ORDERING INFORMATION

Device	Package	Shipping
MC74HC573AN	PDIP±20	1440 / Box
MC74HC573ADW	SOIC±WIDE	38 / Rail
MC74HC573ADWR2	SOIC±WIDE	1000 / Reel
MC74HC573ADT	TSSOP±20	75 / Rail
MC74HC573ADTR2	TSSOP±20	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
May, 2000 ± Rev. 9		MC74HC573A/D

MC74HC573A

LOGIC DIAGRAM

		D0	2				19	Q0
			3				18
		D1						Q1
			4				17
		D2						Q2
DATA			5				16			NONINVERTING
		D3						Q3
			6				15
INPUTS		D4						Q4		OUTPUTS
			7				14
		D5						Q5
			8				13
		D6						Q6
			9				12
		D7						Q7
			11
LATCH ENABLE
			1				PIN 20 = VCC
OUTPUT ENABLE
							PIN 10 = GND

FUNCTION TABLE

	Inputs		Output
Output	Latch
Enable	Enable	D	Q
L	H	H	H
L	H	L	L
L	L	X	No Change
H	X	X	Z

X = Don't Care

Z = High Impedance

Design Criteria	Value	Units
Internal Gate Count*	54.5	ea.
Internal Gate Propagation Delay	1.5	ns
Internal Gate Power Dissipation	5.0	μW
Speed Power Product	0.0075	pJ
*Equivalent to a two±input NAND gate.

PIN ASSIGNMENT

	OUTPUT		1	20	VCC
	ENABLE
	D0		2	19	Q0
	D1		3	18	Q1
	D2		4	17	Q2
	D3		5	16	Q3
	D4		6	15	Q4
	D5		7	14	Q5
	D6		8	13	Q6
	D7		9	12	Q7
	GND		10	11	LATCH
					ENABLE

http://onsemi.com

2

MC74HC573A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, TSSOP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C TSSOP Package: ±6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to	v _	v	_
Symbol	Parameter	Test Conditions	V	_				Unit
				25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1		2.1
			4.5	3.15	3.15		3.15
			6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5		0.5	V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9		0.9
			4.5	1.35	1.35		1.35
			6.0	1.8	1 8		1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9		1.9	V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4		4.4
			6.0	5.9	5.9		5.9
		Vin = VIH or VIL |Iout| ≤ 2.4mA	3.0	2.48	2.34		2.2
		|Iout| v 6.0 mA	4.5	3.98	3.84		3.7
		|Iout| v 7.8 mA	6.0	5.48	5.34		5.2

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

http://onsemi.com

3