MOTOROLA MC74HCT574AFR2, MC74HCT574AFL2, MC74HCT574ADWR2, MC74HCT574AF, MC74HCT574AFEL Datasheet

MC74HCT574A

Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT574A is identical in pinout to the LS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip±flops, but when Output Enable is high, all device outputs are forced to the high±impedance state. Thus, data may be stored even when the outputs are not enabled.

The HCT574A is identical in function to the HCT374A but has the flip±flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.

•Output Drive Capability: 15 LSTTL Loads

•TTL NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 286 FETs or 71.5 Equivalent Gates

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			MARKING
			DIAGRAMS
			20
		PDIP±20	MC74HCT574AN
		N SUFFIX
			AWLYYWW
	20	CASE 738
	1		1
			20
	SOIC WIDE±20		HCT574A
	20	DW SUFFIX
			AWLYYWW
	1	CASE 751D
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT574AN	PDIP±20	1440 / Box
MC74HCT574ADW	SOIC±WIDE	38 / Rail
MC74HCT574ADWR2	SOIC±WIDE	1000 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HCT574A/D

MC74HCT574A

LOGIC DIAGRAM

		D0	2			19	Q0
			3			18
		D1					Q1
			4			17
		D2					Q2
DATA			5			16			NON±
		D3					Q3
			6			15			INVERTING
INPUTS		D4					Q4
									OUTPUTS
		D5	7			14	Q5
			8			13
		D6					Q6
			9			12
		D7					Q7
			11
CLOCK
			1				PIN 20 = VCC
OUTPUT ENABLE							PIN 10 = GND

FUNCTION TABLE

	Inputs		Output
OE	Clock	D	Q
L		H	H
L		L	L
L	L,H,	X	No Change
H	X	X	Z

X = don't care

Z = high impedance

Design Criteria	Value	Units
Internal Gate Count*	71.5	ea
Internal Gate Propagation Delay	1.5	ns
Internal Gate Power Dissipation	5.0	μW
Speed Power Product	0.0075	pJ
*Equivalent to a two±input NAND gate.

PIN ASSIGNMENT

	OUTPUT	1	20	VCC
	ENABLE
	D0	2	19	Q0
	D1	3	18	Q1
	D2	4	17	Q2
	D3	5	16	Q3
	D4	6	15	Q4
	D5	7	14	Q5
	D6	8	13	Q6
	D7	9	12	Q7
	GND	10	11	CLOCK

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MC74HCT574A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
		SOIC Package²		500
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2.0	2.0	2.0	V
	Voltage	|Iout| v 20 μA	5.5	2.0	2.0	2.0
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8	0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8	0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4	4.4
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4	5.4
		Vin = VIH or VIL					V
		|Iout| v 6.0 mA	4.5	3.98	3.84	3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1	0.1
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1	0.1
		Vin = VIH or VIL
		|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND	5.5	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND
	Current (per Package)	Iout = 0 μA	5.5	4.0	40	160	μA

1. Output in high±impedance state.

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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