MOTOROLA MC74HC273AFR2, MC74HC273AH, MC74HC273AN, MC74HC273AFEL, MC74HC273AFL1 Datasheet

MC74HCT273A

Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs

High±Performance Silicon±Gate CMOS

The MC74HCT273A may be used as a level converter for interfacing TTL or NMOS outputs to High±Speed CMOS inputs.

The HCT273A is identical in pinout to the LS273.

This device consists of eight D flip±flops with common Clock and Reset inputs. Each flip±flop is loaded with a low±to±high transition of the Clock input. Reset is asynchronous and active low.

•Output Drive Capability: 10 LSTTL Loads

•TTL/NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 284 FETs or 71 Equivalent Gates

LOGIC DIAGRAM

		D0	3					2		Q0
								5
			4							Q1
		D1
								6
			7
		D2								Q2
DATA			8					9
		D3
										Q3	NONINVERTING
			13
INPUTS								12
		D4								Q4	OUTPUTS
			14
		D5						15		Q5
			17
		D6						16
			18							Q6
		D7
								19
	CLOCK		11							Q7
			1					PIN 20 = VCC
	RESET							PIN 10 = GND
				FUNCTION TABLE
				Inputs				Output
		Reset			Clock	D		Q
			L		X	X		L
			H			H		H
			H			L		L
			H		L	X	No Change
			H			X	No Change

X = Don't Care

Z = High Impedance

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			MARKING
			DIAGRAMS
			20
		PDIP±20	MC74HCT273AN
		N SUFFIX
			AWLYYWW
	20	CASE 738
	1		1
			20
	SOIC WIDE±20		HCT273A
	20	DW SUFFIX
			AWLYYWW
	1	CASE 751D
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

PIN ASSIGNMENT

RESET	1	20	VCC
Q0	2	19	Q7
D0	3	18	D7
D1	4	17	D6
Q1	5	16	Q6
Q2	6	15	Q5
D2	7	14	D5
D3	8	13	D4
Q3	9	12	Q4
GND	10	11	CLOCK

ORDERING INFORMATION

Device	Package	Shipping
MC74HCT273AN	PDIP±20	1440 / Box
MC74HCT273ADW	SOIC±WIDE	38 / Rail
MC74HCT273ADWR2	SOIC±WIDE	1000 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HCT273A/D

MC74HCT273A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(SOIC or Plastic DIP)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C		Unit
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2.0	2.0		2.0	V
	Voltage	|Iout| v 20 μA	5.5	2.0	2.0		2.0
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8		0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8		0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4		4.4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4		5.4
		Vin = VIH or VIL	4.5	3.98	3.84		3.7
		|Iout| v 4.0 mA
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1		0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1		0.1
		Vin = VIH or VIL
		|Iout| v 4.0 mA	4.5	0.26	0.33		0.4
Iin	Maximum Input Leakage	Vin = VCC or GND	5.5	± 0.1	± 1.0		± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4.0	40		160	μA
	Current (per Package)	Iout = 0 μA
ICC	Additional Quiescent Supply	Vin = 2.4 V, Any One Input		≥ ±55_C	25_C to 125_C
	Current	Vin = VCC or GND, Other Inputs
		lout = 0 μA	5.5	2.9	2.4			mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HCT273A

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
			± 55 to
Symbol	Parameter	Fig.	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	1, 4	30	24	20	MHz
tPLH,	Maximum Propagation Delay, Clock to Q	1, 4	25	28	35	ns
tPHL
tPHL	Maximum Propagation Delay, Reset to Q	2, 4	25	28	35	ns
tTLH,	Maximum Output Transition Time, Any Output	1, 5	18	20	22	ns
tTHL

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Gate)*	30	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

					Guaranteed Limit
			± 55 to 25_C			v 85_C				v 125_C
Symbol	Parameter	Fig.											Unit
			Min	Max		Min	Max			Min	Max
tsu	Minimum Setup Time, Data to Clock	3	10			12				15			ns
th	Minimum Hold Time, Clock to Data	3	3.0			3.0				3.0			ns
trec	Minimum Recovery Time, Set or Reset Inactive to Clock	2	5.0			5.0				5.0			ns
tw	Minimum Pulse Width, Clock	1	12			15				18			ns
tw	Minimum Pulse Width, Set or Reset	2	12			15				18			ns
tr, tf	Maximum Input Rise and Fall Times	1		500			500				500		ns

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