MOTOROLA MC74HC393FL2, MC74HC393FR1, MC74HC393FR2, MC74HC393FEL, MC74HC393DTR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual 4-Stage

Binary Ripple Counter

High±Performance Silicon±Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 4±bit binary ripple counters with parallel outputs from each counter stage. A 256 counter can be obtained by cascading the two binary counters.

Internal flip±flops are triggered by high±to±low transitions of the clock input. Reset for the counters is asynchronous and active±high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

					3, 11	Q1
					4, 10
	1, 13		BINARY			Q2
CLOCK					5, 9
			COUNTER			Q3
					6, 8
						Q4
RESET	2, 12
		PIN 14 = VCC
		PIN 7 = GND

MC54/74HC393

		J SUFFIX
	CERAMIC PACKAGE
	14	CASE 632±08
	1
		N SUFFIX
	14	PLASTIC PACKAGE
		CASE 646±06
	1
		D SUFFIX
	14	SOIC PACKAGE
	1	CASE 751A±03
	ORDERING INFORMATION
	MC54HCXXXJ	Ceramic
	MC74HCXXXN	Plastic
	MC74HCXXXD	SOIC

PIN ASSIGNMENT

CLOCK a	1	14	VCC
RESET a	2	13	CLOCK b
Q1a	3	12	RESET b
Q2a	4	11	Q1b
Q3a	5	10	Q2b
Q4a	6	9	Q3b
GND	7	8	Q4b
FUNCTION TABLE
Inputs
Clock	Reset		Outputs
X	H		L
H	L	No Change
L	L	No Change
	L	No Change
	L	Advance to
			Next State

10/95

Motorola, Inc. 1995

REV 6

MC54/74HC393

MAXIMUM RATINGS*

	Symbol	Parameter	Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)	± 1.5 to VCC + 1.5	V
	Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin	± 20	mA
	Iout	DC Output Current, per Pin	± 25	mA
	ICC	DC Supply Current, VCC and GND Pins	± 50	mA
	PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
		SOIC Package²	500
	Tstg	Storage Temperature	± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds	260	_C
		(Plastic or SOIC DIP)
		(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to	v _	v	_
Symbol	Parameter	Test Conditions		V	_				Unit
					25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA		4.5	3.15	3.15		3.15
				6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.3	0.3		0.3	V
	Voltage	|Iout| v 20 μA		4.5	0.9	0.9		0.9
				6.0	1.2	1.2		1.2
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9		1.9	V
	Voltage	|Iout| v 20 μA		4.5	4.4	4.4		4.4
				6.0	5.9	5.9		5.9
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	3.98	3.84		3.70
			|Iout| v 5.2 mA	6.0	5.48	5.34		5.20
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1		0.1	V
	Voltage	|Iout| v 20 μA		4.5	0.1	0.1		0.1
				6.0	0.1	0.1		0.1
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	0.26	0.33		0.40
			|Iout| v 5.2 mA	6.0	0.26	0.33		0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND		6.0	± 0.1	± 1.0		± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	8	80		160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

2

MC54/74HC393

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C		Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	5.4	4.4	3.6		MHz
	(Figures 1 and 3)	4.5	27	22	18
		6.0	32	26	21
tPLH,	Maximum Propagation Delay, Clock to Q1	2.0	120	150	180		ns
tPHL	(Figures 1 and 3)	4.5	24	30	36
		6.0	20	26	31
tPLH,	Maximum Propagation Delay, Clock to Q2	2.0	190	240	285		ns
tPHL	(Figures 1 and 3)	4.5	38	48	57
		6.0	32	41	48
tPLH,	Maximum Propagation Delay, Clock to Q3	2.0	240	300	360		ns
tPHL	(Figures 1 and 3)	4.5	48	60	72
		6.0	41	51	61
tPLH,	Maximum Propagation Delay, Clock to Q4	2.0	290	365	435		ns
tPHL	(Figures 1 and 3)	4.5	58	73	87
		6.0	49	62	74
tPHL	Maximum Propagation Delay, Reset to any Q	2.0	165	205	250		ns
	(Figures 2 and 3)	4.5	33	41	50
		6.0	28	35	43
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110		ns
tTHL	(Figures 1 and 3)	4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10		pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
			Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Counter)*			40			pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
trec	Minimum Recovery Time, Reset Inactive to Clock	2.0	50	65	75	ns
	(Figure 2)	4.5	10	13	15
		6.0	9	11	13
tw	Minimum Pulse Width, Clock	2.0	80	100	120	ns
	(Figure 1)	4.5	16	20	24
		6.0	14	17	20
tw	Minimum Pulse Width, Reset	2.0	125	155	190	ns
	(Figure 2)	4.5	25	31	38
		6.0	21	26	32
tr, tf	Maximum Input Rise and Fall Times	2.0	1000	1000	1000	ns
	(Figure 1)	4.5	500	500	500
		6.0	400	400	400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

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MOTOROLA