Synchronous Presettable
BCD Decade Counter
The MC74AC160/74ACT160 and MC74AC162/74ACT162 are high-speed synchronous decade counters operating in the BCD (8421) sequence. They
are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC160/74ACT160 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC162/74ACT162 has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock.
•Synchronous Counting and Loading
•High-Speed Synchronous Expansion
•Typical Count Rate of 120 MHz
•Outputs Source/Sink 24 mA
•′ACT160 and ′ACT162 Have TTL Compatible Inputs
VCC |
TC |
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Q0 |
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Q1 |
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Q2 |
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Q3 |
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CET |
PE |
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15 |
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9 |
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*R |
CP |
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P0 |
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P1 |
P2 |
P3 |
CEP |
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GND |
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PIN NAMES |
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CEP |
Count Enable Parallel Input |
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CET |
Count Enable Trickle Input |
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CP |
Clock Pulse Input |
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MR |
(′160) Asynchronous Master Reset Input |
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SR |
(′162) Synchronous Reset Input |
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P0 |
±P3 |
Parallel Data Inputs |
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PE |
Parallel Enable Input |
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Q0±Q3 |
Flip-Flop Outputs |
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TC |
Terminal Count Output |
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MC74AC160
MC74ACT160
MC74AC162
MC74ACT162
SYNCHRONOUS
PRESETTABLE
BCD DECADE COUNTER
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
PE P0 P1 P2 P3
CEP
CET TC
CP
*R Q0 Q1 Q2 Q3
*MR for ′160 *SR for ′162
FACT DATA
5-1
MC74AC160 MC74ACT160 MC74AC162 MC74ACT162
FUNCTIONAL DESCRIPTION
The MC74AC160/74ACT160 and MC74AC162/74ACT162 count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ′160) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (′160), synchronous reset (′162), parallel load, count-up and hold. Five control inputs Ð Master Reset (MR, ′160), Synchronous Reset (SR,′162), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) Ð determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (′160) or SR (′162) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.
MODE SELECT TABLE
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Action on the Rising |
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*SR |
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PE |
CET |
CEP |
Clock Edge ( |
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L |
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X |
X |
X |
Reset (Clear) |
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H |
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L |
X |
X |
Load (Pn → Qn) |
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H |
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H |
H |
H |
Count (Increment) |
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H |
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H |
L |
X |
No Change (Hold) |
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H |
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H |
X |
L |
No Change (Hold) |
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*For ′162 only
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
The MC74AC160/74ACT160 and MC74AC162/74ACT162 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the MC74AC160/74ACT160 and MC74AC162/74ACT162 decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram.
Logic Equations: Count Enable = CEP• CET•PE
TC = Q0• Q1• Q2• Q3•CET
STATE DIAGRAM
0 1 2 3 4
15 |
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5 |
14 |
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6 |
13 |
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7 |
12 |
11 |
10 |
9 |
8 |
FACT DATA
5-2
MC74AC160 MC74ACT160 MC74AC162 MC74ACT162
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LOGIC DIAGRAM |
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P0 |
P1 |
P2 |
P3 |
PE |
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′160 |
′162 |
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CEP |
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CET |
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′162 |
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ONLY |
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TC |
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CP |
CP |
′160 |
CP |
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ONLY |
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D |
CP |
D |
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CD |
Q |
Q |
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Q0 |
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Q0 |
DETAIL A |
DETAIL A |
DETAIL A |
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DETAIL A |
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MR ′160 |
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SR ′162 |
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Q0 |
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Q1 |
Q2 |
Q3 |
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
±0.5 to +7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Iin |
DC Input Current, per Pin |
±20 |
mA |
Iout |
DC Output Sink/Source Current, per Pin |
±50 |
mA |
ICC |
DC VCC or GND Current per Output Pin |
±50 |
mA |
Tstg |
Storage Temperature |
±65 to +150 |
°C |
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
FACT DATA
5-3
MC74AC160 MC74ACT160 MC74AC162 MC74ACT162
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
′AC |
2.0 |
5.0 |
6.0 |
V |
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′ACT |
4.5 |
5.0 |
5.5 |
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Vin, Vout |
DC Input Voltage, Output Voltage (Ref. to GND) |
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0 |
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VCC |
V |
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Input Rise and Fall Time (Note 1) |
VCC @ 3.0 V |
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150 |
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tr, tf |
VCC @ 4.5 V |
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40 |
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ns/V |
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′AC Devices except Schmitt Inputs |
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VCC @ 5.5 V |
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25 |
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tr, tf |
Input Rise and Fall Time (Note 2) |
VCC @ 4.5 V |
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10 |
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ns/V |
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′ACT Devices except Schmitt Inputs |
VCC @ 5.5 V |
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8.0 |
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TJ |
Junction Temperature (PDIP) |
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140 |
°C |
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TA |
Operating Ambient Temperature Range |
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±40 |
25 |
85 |
°C |
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IOH |
Output Current Ð High |
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±24 |
mA |
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IOL |
Output Current Ð Low |
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24 |
mA |
1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
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74AC |
74AC |
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Symbol |
Parameter |
VCC |
TA = +25°C |
TA = |
Unit |
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Conditions |
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(V) |
±40°C to +85°C |
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Typ |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
1.5 |
2.1 |
2.1 |
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VOUT = 0.1 V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
3.15 |
V |
or VCC ± 0.1 V |
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5.5 |
2.75 |
3.85 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
1.5 |
0.9 |
0.9 |
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VOUT = 0.1 V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
1.35 |
V |
or VCC ± 0.1 V |
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5.5 |
2.75 |
1.65 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.99 |
2.9 |
2.9 |
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IOUT = ±50 mA |
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Output Voltage |
4.5 |
4.49 |
4.4 |
4.4 |
V |
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5.5 |
5.49 |
5.4 |
5.4 |
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*VIN = VIL or VIH |
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3.0 |
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2.56 |
2.46 |
V |
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±12 mA |
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4.5 |
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3.86 |
3.76 |
IOH |
±24 mA |
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5.5 |
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4.86 |
4.76 |
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±24 mA |
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VOL |
Maximum Low Level |
3.0 |
0.002 |
0.1 |
0.1 |
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IOUT = 50 mA |
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Output Voltage |
4.5 |
0.001 |
0.1 |
0.1 |
V |
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5.5 |
0.001 |
0.1 |
0.1 |
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*VIN = VIL or VIH |
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3.0 |
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0.36 |
0.44 |
V |
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12 mA |
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4.5 |
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0.36 |
0.44 |
IOL |
24 mA |
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5.5 |
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0.36 |
0.44 |
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24 mA |
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IIN |
Maximum Input |
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μ |
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Leakage Current |
5.5 |
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0.1 |
1.0 |
A |
VI = VCC, GND |
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IOLD |
²Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65 V Max |
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Output Current |
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IOHD |
5.5 |
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±75 |
mA |
VOHD = 3.85 V Min |
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ICC |
Maximum Quiescent |
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μ |
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Supply Current |
5.5 |
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8.0 |
80 |
A |
VIN = VCC or GND |
* All outputs loaded; thresholds on input associated with output under test. ² Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
FACT DATA
5-4
MC74AC160 MC74ACT160 MC74AC162 MC74ACT162
MC74AC160
AC CHARACTERISTICS (For Figures and Waveforms Ð See Section 3)
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74AC160 |
74AC160 |
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VCC* |
TA = +25°C |
TA = ±40°C |
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Fig. |
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Symbol |
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Parameter |
to +85°C |
Unit |
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(V) |
CL = 50 pF |
No. |
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CL = 50 pF |
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Min |
Max |
Min |
Max |
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fmax |
Maximum Count |
3.3 |
65 |
Ð |
60 |
Ð |
MHz |
3-3 |
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Frequency |
5.0 |
110 |
Ð |
95 |
Ð |
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tPLH |
Propagation Delay |
3.3 |
2.0 |
12.0 |
1.5 |
14.0 |
ns |
3-6 |
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CP to Qn |
(PE Input HIGH) |
5.0 |
1.5 |
9.0 |
1.0 |
10.5 |
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tPHL |
Propagation Delay |
3.3 |
2.0 |
12.0 |
1.5 |
14.0 |
ns |
3-6 |
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CP to Qn |
(PE Input HIGH) |
5.0 |
1.5 |
9.0 |
1.5 |
10.5 |
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tPLH |
Propagation Delay |
3.3 |
2.0 |
12.0 |
1.5 |
14.0 |
ns |
3-6 |
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CP to Qn |
(PE Input LOW) |
5.0 |
1.5 |
9.0 |
1.0 |
10.5 |
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tPHL |
Propagation Delay |
3.3 |
2.0 |
12.0 |
1.5 |
14.0 |
ns |
3-6 |
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CP to Qn |
(PE Input LOW) |
5.0 |
1.5 |
9.0 |
1.5 |
10.5 |
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tPLH |
Propagation Delay |
3.3 |
3.0 |
15.0 |
2.5 |
17.5 |
ns |
3-6 |
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CP to TC |
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5.0 |
2.0 |
11.0 |
1.5 |
12.5 |
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tPHL |
Propagation Delay |
3.3 |
3.5 |
14.5 |
2.5 |
16.5 |
ns |
3-6 |
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CP to TC |
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5.0 |
2.0 |
11.0 |
2.0 |
12.5 |
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tPLH |
Propagation Delay |
3.3 |
2.0 |
10.5 |
1.5 |
12.5 |
ns |
3-6 |
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CET to TC |
5.0 |
1.5 |
7.5 |
1.0 |
9.0 |
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tPHL |
Propagation Delay |
3.3 |
2.5 |
11.5 |
2.0 |
13.5 |
ns |
3-6 |
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CET to TC |
5.0 |
2.0 |
9.0 |
1.5 |
10.5 |
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tPHL |
Propagation Delay |
3.3 |
2.0 |
12.0 |
1.5 |
13.5 |
ns |
3-6 |
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MR to Qn |
(′AC160) |
5.0 |
1.5 |
9.5 |
1.0 |
10.0 |
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tPHL |
Propagation Delay |
3.3 |
3.5 |
15.0 |
3.0 |
17.0 |
ns |
3-6 |
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MR to TC |
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5.0 |
2.5 |
12.0 |
2.0 |
13.5 |
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*Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-5