August 1989
Revised August 2000
100301
Low Power Triple 5-Input OR/NOR Gate
General Description
The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered.
Features
■23% power reduction of the 100101
■2000V ESD protection
■Pin/function compatible with 100101
■Voltage compensated operating range = − 4.2V to − 5.7V
■Available to industrial grade temperature range (PLCC package only)
Ordering Code:
Order Number |
Package Number |
Package Description |
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100301SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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100301PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100301QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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100301QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Industrial Temperature Range (− 40° C to + 85° C) |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagrams |
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24-Pin DIP/SOIC |
28-Pin PLCC
Pin Descriptions
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Pin Names |
Description |
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Dna, Dnb, Dnc |
Data Inputs |
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Oa, Ob, Oc |
Data Outputs |
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b, |
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c |
Complementary Data Outputs |
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O |
a, |
O |
O |
Gate OR/NOR Input-5 Triple Power Low 100301
© 2000 Fairchild Semiconductor Corporation |
DS010579 |
www.fairchildsemi.com |
100301
Truth Table
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Outputs |
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D1a, D1b, D1c |
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D2a, D2b, D2c |
D3a, D3b, D3c |
D4a, D4b, D4c |
D5a, D5b, D5c |
Oa, Ob, Oc |
Oa, Ob, Oc |
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L |
H = HIGH Voltage Level
L = LOW Voltage Level
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature (TJ) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
Input Voltage (DC) |
VEE to + 0.5V |
Output Current (DC Output HIGH) |
− 50 mA |
ESD (Note 2) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
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Commercial |
0° C to + 85° C |
Industrial |
− 40° C to + 85° C |
Supply Voltage (VEE) |
− 5.7V to − 4.2V |
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “recommended Operating Conditions” table will define the conditions for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 3)
VEE = − 4.2V to − 5.7V, VCC = VCCA = |
GND, TC = |
0° C to + 85° C |
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Symbol |
Parameter |
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Min |
Typ |
Max |
Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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− 1025 |
− 955 |
− 870 |
mV |
VIN = |
VIH(Max) |
or VIL(Min) |
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Loading with |
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VOL |
Output LOW Voltage |
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− 1830 |
− 1705 |
− 1620 |
mV |
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50Ω |
to − 2.0V |
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VOHC |
Output HIGH Voltage |
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− 1035 |
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mV |
VIN = |
VIH(Min) or VIL(Max) |
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Loading with |
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VOLC |
Output LOW Voltage |
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− 1610 |
mV |
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50Ω |
to − 2.0V |
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VIH |
Input HIGH Voltage |
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− 1165 |
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− 870 |
mV |
Guaranteed HIGH Signal for All Inputs |
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VIL |
Input LOW Voltage |
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− 1830 |
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− 1475 |
mV |
Guaranteed LOW Signal for All Inputs |
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IIL |
Input LOW Current |
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0.50 |
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µ A |
VIN = |
VIL(Min) |
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IIH |
Input HIGH Current |
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240 |
µ A |
VIN = |
VIH(Max) |
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IEE |
Power Supply Current |
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− 29 |
− 17 |
− 15 |
mA |
Inputs OPEN |
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Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
DIP AC Electrical Characteristics
VEE = − |
4.2V to − 5.7V, VCC = VCCA = GND |
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Symbol |
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Parameter |
TC = 0° C |
TC = + 25° C |
TC |
= + 85° C |
Units |
Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPLH |
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Propagation Delay |
0.50 |
1.10 |
0.50 |
1.15 |
0.50 |
1.20 |
ns |
Figures 1, 2 |
tPHL |
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Data to Output |
(Note 4) |
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tTLH |
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Transition Time |
0.40 |
1.20 |
0.40 |
1.20 |
0.40 |
1.20 |
ns |
Figures 1, 2 |
tTHL |
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20% to 80%, 80% to 20% |
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Note 4: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching.
100301
3 |
www.fairchildsemi.com |