Fairchild Semiconductor 100314SCX, 100314SC, 100314QIX, 100314QI, 100314QCX Datasheet

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Fairchild Semiconductor 100314SCX, 100314SC, 100314QIX, 100314QI, 100314QCX Datasheet

February 1990

Revised August 2000

100314

Low Power Quint Differential Line Receiver

General Description

The 100314 is a monolithic quint differential line receiver with emitter-follower outputs. An internal reference supply (VBB) is available for single-ended reception. When used in single-ended operation the apparent input threshold of the true inputs is 25 mV to 30 mV higher (positive) than the threshold of the complementary inputs. Unlike other F100K ECL devices, the inputs do not have input pull-down resistors.

Active current sources provide common-mode rejection of 1.0V in either the positive or negative direction. A defined output state exists if both inverting and non-inverting inputs are at the same potential between VEE and VCC. The

defined state is logic HIGH on the Oa–Oe outputs.

Features

35% power reduction of the 100114

2000V ESD protection

Pin/function compatible with 100114

Voltage compensated operating range = − 4.2V to − 5.7V

Available to industrial grade temperature range (PLCC package only)

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

100314SC

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

 

 

 

100314PC

N24E

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

 

 

 

100314QC

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

 

100314QI

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

Industrial Temperature Range (− 40° C to + 85° C)

 

 

 

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagrams

 

24-Pin DIP/SOIC

28-Pin PLCC

Pin Descriptions

 

 

Pin Names

Description

 

 

 

 

Da–De

Data Inputs

 

 

 

 

 

 

 

D

a–D

e

Inverting Data Inputs

 

Oa–Oe

Data Outputs

 

 

 

 

e

Complementary Data Outputs

 

O

a–O

Receiver Line Differential Quint Power Low 100314

© 2000 Fairchild Semiconductor Corporation

DS010260

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100314

Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)

− 65° C to + 150° C

Maximum Junction Temperature (TJ)

+ 150° C

Pin Potential to Ground Pin (VEE)

− 7.0V to + 0.5V

Input Voltage (DC)

VEE to + 0.5V

Output Current (DC Output HIGH)

− 50 mA

ESD (Note 2)

≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)

 

Commercial

0° C to + 85° C

Industrial

− 40° C to + 85° C

Supply Voltage (VEE)

− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = − 4.2V to − 5.7V, VCC = VCCA =

GND, TC = 0° C to +

85° C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Min

 

Typ

Max

Units

 

 

 

 

 

 

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

 

− 1025

 

− 955

− 870

mV

 

VIN =

VIH (Max)

 

Loading with

VOL

Output LOW Voltage

 

− 1830

 

− 1705

− 1620

mV

or VIL (Min)

 

50Ω

to − 2.0V

VOHC

Output HIGH Voltage

 

− 1035

 

 

 

mV

 

VIN =

VIH

 

Loading with

VOLC

Output LOW Voltage

 

 

 

 

− 1610

mV

or VIL (Max)

 

50Ω

to − 2.0V

VBB

Output Reference Voltage

 

− 1380

 

− 1320

− 1260

mV

 

IVBB =

250 µ A

 

 

 

VDIFF

Input Voltage Differential

 

150

 

 

 

mV

 

Required for Full Output Swing

 

VCM

Common Mode Voltage

 

VCC − 2.0

 

 

VCC − 0.5

V

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH

Single-Ended

 

 

 

 

 

 

 

Guaranteed HIGH Signal for All

 

 

Input HIGH Voltage

 

− 1110

 

 

− 870

mV

Inputs (with one input tied to VBB)

 

 

 

 

 

 

 

 

 

VBB (Max) + VDIFF

 

 

 

VIL

Single-Ended

 

 

 

 

 

 

 

Guaranteed LOW Signal for All

 

 

Input LOW Voltage

 

− 1830

 

 

− 1530

mV

Inputs (with one input tied to VBB)

 

 

 

 

 

 

 

 

 

VBB (Min) − VDIFF

 

 

 

IIL

Input LOW Current

 

0.50

 

 

 

µ A

 

VIN =

VIL (Min)

 

 

 

IIH

Input HIGH Current

 

 

 

 

240

µ A

 

VIN =

VIH (Max), Da–De =

VBB,

 

 

 

 

 

 

 

 

 

 

 

 

 

e =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

a–D

VIL(Min)

 

 

 

ICBO

Input Leakage Current

 

− 10

 

 

 

µ A

 

VIN =

VEE, Da–De = VBB,

 

 

 

 

 

 

 

 

 

 

 

 

 

e =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

a–D

VIL (Min)

 

 

 

 

 

 

− 60

 

 

− 30

 

 

Da–De =

VBB,

 

 

 

e =

 

 

 

IEE

Power Supply Current

 

 

 

mA

 

D

a–D

VIL (Min)

 

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

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2

Commercial Version (Continued)

DIP AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA = GND

Symbol

Parameter

TC = 0° C

TC = + 25° C

TC = + 85° C

Units

Conditions

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

fMAXFS

Toggle Frequency

250

 

250

 

250

 

MHz

(Note 2)

 

(Full Swing)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fMAXRS

Toggle Frequency

700

 

700

 

700

 

MHz

(Note 3)

 

(Reduced Swing)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

0.65

1.90

0.65

2.00

0.70

2.00

ns

 

tPHL

Data to Output

 

 

 

 

 

 

 

 

Figures 1, 2

tTLH

Transition Time

0.35

1.20

0.35

1.20

0.35

1.20

ns

 

tTHL

20% to 80%, 80% to 20%

 

 

 

 

 

 

 

 

 

SOIC and PLCC AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA = GND

Symbol

Parameter

TC = 0° C

TC = + 25° C

TC = + 85° C

Units

Conditions

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

fMAXFS

Toggle Frequency

250

 

250

 

250

 

MHz

(Note 4)

 

(Full Swing)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fMAXRS

Toggle Frequency

700

 

700

 

700

 

MHz

(Note 5)

 

(Reduced Swing)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

0.65

1.70

0.65

1.80

0.70

1.80

ns

 

tPHL

Data to Output

 

 

 

 

 

 

 

 

Figures 1, 2

tTLH

Transition Time

0.35

1.10

0.35

1.10

0.35

1.10

ns

 

tTHL

20% to 80%, 80% to 20%

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

0.70

1.50

0.80

1.60

0.90

1.80

ns

PLCC only

tPHL

Data to Output

 

 

 

 

 

 

 

 

tOSHL

Maximum Skew Common Edge

 

 

 

 

 

 

 

PLCC only

 

Output-to-Output Variation

 

280

 

280

 

280

ps

(Note 6)(Note 7)

 

Data to Output Path

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOSLH

Maximum Skew Common Edge

 

 

 

 

 

 

 

PLCC only

 

Output-to-Output Variation

 

330

 

330

 

330

ps

(Note 6)(Note 7)

 

Data to Output Path

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOST

Maximum Skew Opposite Edge

 

 

 

 

 

 

 

PLCC only

 

Output-to-Output Variation

 

330

 

330

 

330

ps

(Note 6)(Note 7)

 

Data to Output Path

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPS

Maximum Skew

 

 

 

 

 

 

 

PLCC only

 

Pin (Signal) Transition Variation

 

320

 

320

 

320

ps

(Note 6)(Note 7)

 

Data to Output Path

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 4: Maximum toggle frequency at which VOH and VOL DC specifications are maintained.

Note 5: Maximum toggle frequency at which outputs maintain 150 mV swing.

Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.

Note 7: All skews calculated using input crossing point to output crossing point propagation delays.

100314

3

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