ANALOG DEVICES CN-0279 Service Manual

Circuit Note

CN-0279

Circuits from the Lab™ reference circuits are engineered and tested for quick and easysystem integrationto helpsolve today’s analog, mixed-signal, and RF design challenges. For more informationand/or support, visit www.analog.com/CN0279.

Devices Connected/Referenced

	AD9642	14-Bit, 250 MSPS Analog-to-Digital Converter
	ADL5565	6 GHz Ultrahigh Dynamic Range Differential
		Amplifier

High IF Sampling Receiver Front End with Band-Pass Filter

EVALUATION AND DESIGN SUPPORT

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to- digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spuriousfree dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

CIRCUIT DESCRIPTION

The circuit accepts a single-ended input and converts it to differential input using a wide bandwidth (3 GHz) Mini-Circuits TC2-1T 1:2 transformer. The 6 GHz ADL5565 differential amplifier has a differential input impedance of 200 Ω when operating at a gain of 6 dB, and 100 Ω when operating at a gain of 12 dB. A gain option of 15.5 dB is also available.

The ADL5565 is an ideal driver for the AD9642, and the fully differential architecture through the band-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products. The ADL5565 provides a gain of 6 dB or 12 dB, depending on the input connection. In the circuit, a gain of 12 dB was used to compensate for the insertion loss of the filter network and transformer (approximately 5.8 dB), providing an overall signal gain of 5.5 dB.

0.5dB LOSS

	ANALOG
	INPUT	XFMR
	+1.5dBm FS
	AT 127MHz	1:2 Z
		TC2-1T
	INPUT
	Z = 50Ω

OVERALL

GAIN = 5.5dB

11.8dB GAIN

+3.3V

0.1µF
	VIP2
	VIP1
ZI = 100Ω
	VIN1
0.1µF	VIN2

15Ω 0.1µF

5Ω

ADL5565

G = 12dB

5Ω

15Ω 0.1µF

217Ω

5.8dB LOSS
5.6dB LOSS		0.2dB LOSS
				+1.8V	+1.8V
				AVDD	DRVDD
1.2pF	620nH		5Ω		AD9642
		100Ω			14-BIT
36nH					205MSPS
		0.1µF			ADC
33pF	36nH		33pF
				2.5pF
			2.85kΩ
		100Ω		INTERNAL
1.2pF				INPUT Z
	620nH		5Ω
			FS = 1.75V
40Ω	187Ω		p-p DIFF
			VCM

Figure 1. 14-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values for an Input Frequency of 127 MHz

10823-001

Rev. 0

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CN-0279

An input signal of 1.5 dBm produces a full-scale 1.75 V p-p differential signal at the ADC input.

The antialiasing filter is a third-order, Butterworth filter designed with a standard filter design program. A Butterworth filter was chosen because of its pass-band flatness. A third-order filter yields an ac noise bandwidth ratio of 1.05 and can be designed with the aid of several free filter programs such as Nuhertz Technologies Filter Free, or the quite universal circuit simulator (Qucs) free simulation.

To achieve best performance, load the ADL5565 with a net differential load of 200 Ω. The 15 Ω series resistors isolate the filter capacitance from the amplifier output, and the 100 Ω resistors in parallel with the downstream impedance yield a net load impedance of 217 Ω when added to the 30 Ω series resistance.

The 5 Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier.

The 2.85 kΩ input impedance was determined using the downloadable spreadsheet on the AD9642 webpage. Simply use the parallel track mode values at the center of the IF frequency of interest. The spreadsheet shows both the real and imaginary values.

The third-order, Butterworth filter was designed with a source impedance (differential) of 200 Ω, a load impedance (differential) of 200 Ω, a center frequency of 127 MHz, and a 3 dB bandwidth of 20 MHz. The calculated values from a standard filter design program are shown in Figure 1. Because of the high values of series inductance required, the 1.59 µH inductors were decreased to 620 nH, and the 0.987 pF capacitors increased proportionally to 2.53 pF, thereby maintaining the same resonant frequency of 127 MHz, with more realistic component values.

		(2.53pF)	(620nH)
	100Ω	0.987pF	1.59µH
+
–	39.8pF	39.5nH	39.8pF	39.5nH	200Ω
	100Ω
					002-
		(2.53pF)	(620nH)
					10443
		0.987pF	1.59µH

Figure 2. Starting Design for Third-Order, Differential Butterworth Filter with ZS = 200 Ω, ZL = 200 Ω, FC = 127 MHz, and BW = 20 MHz

The internal 2.5 pF capacitance of the ADC was subtracted from the value of the second shunt capacitor to yield a value of 37.3 pF. In the circuit, this capacitor was located near the ADC to reduce/absorb the charge kickback.

The values chosen for the final filter passive components (after adjusting for actual circuit parasitics) are shown in Figure 1.

Circuit Note

The measured performance of the system is summarized in Table 1, where the 3 dB bandwidth, 18 MHz centered at 127 MHz. The total insertion loss of the network is approximately 5.8 dB. The frequency response is shown in Figure 3, and the SNR and SFDR performance are shown in Figure 4.

Table 1. Measured Performance of the Circuit

Performance Specifications at −1 dBFS
(FS = 1.75V p-p), Sample Rate = 205 MSPS																Final Results
Center Frequency																127 MHz
Pass-Band Flatness (118 MHz to 136 MHz)																3 dB
SNRFS at 127 MHz																71.7 dBFS
SFDR at 127 MHz																92 dBc
H2/H3 at 127 MHz																93 dBc/92 dBc
Overall Gain at 127 MHz																5.5 dB
Input Drive at 127 MHz																0.5 dBm (−1 dBFS)
	0
	–5
(dBFS)	–10
	–15
AMPLITUDE
	–20
	–25
	–30
	–35
	–4050																						-003
				100									150			200		250			300
					ANALOG INPUT FREQUENCY (MHz)																		10823
	Figure 3. Pass-Band Flatness Performance vs. Frequency
	95
						SFDR				(dBc)
	90
(dBc)	85
	80
SFDR	75
						SNR (dBFS)
(dBFS),
	70
SNR
	65
	60
	55
	50																						-004
	118 120			122 124 126 128									130			132		134			136
				ANALOG INPUT FREQUENCY (MHz)																			10823

Figure 4. SNR/SFDR Performance vs. Frequency, Sample Rate = 205 MSPS

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