Analog Devices AD1845JST, AD1845JP-REEL, AD1845JP, AD1845 Datasheet

a		Parallel-Port 16-Bit
		SoundPort® Stereo Codec
		AD1845

FEATURES

Single-Chip Integrated åD Digital Audio Stereo Codec

Microsoft® and Windows® Sound System Compatible MPC Level-2+ Compliant Mixing

16 mA Bus Drive Capability

Supports Two DMA Channels for Full Duplex Operation On-Chip Capture and Playback FIFOs

Advanced Power-Down Modes Programmable Gain and Attenuation

Sample Rates from 4.0 kHz to 50 kHz Derived from a Single Clock or Crystal Input

68-Lead PLCC, 100-Lead TQFP Packages Operation from +5 V Supplies

Byte-Wide Parallel Interface to ISA and EISA Buses Pin Compatible with AD1848, AD1846, CS4248, CS4231

PRODUCT OVERVIEW

The Parallel Port AD1845 SoundPort Stereo Codec integrates key audio data conversion and control functions into a single integrated circuit. The AD1845 provides a complete, single chip computer audio solution for business audio and multimedia applications. The codec includes stereo audio converters, com-

plete on-chip filtering, MPC Level-2 compliant analog mixing, programmable gain, attenuation and mute, a variable sample frequency generator, FIFOs, and supports advanced powerdown modes. It provides a direct, byte-wide interface to both ISA (“AT”) and EISA computer buses for simplified implementation on a computer motherboard or add-in card.

The AD1845 SoundPort Stereo Codec supports a DMA request/grant architecture for transferring data with the host computer bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for control register accesses and for applications lacking DMA control. Two input control lines support mixed direct and indirect addressing of thirty-seven internal control registers over this asynchronous interface. The AD1845 includes dual DMA count registers for full duplex operation enabling the AD1845 to capture data on one DMA channel and play back data on a separate channel. The FIFOs on the AD1845 reduce the risk of losing data when making DMA transfers over the ISA/EISA bus. The FIFOs buffer data transfers and allow for relaxed timing in acknowledging requests for capture and playback data.

(Continued on Page 9)

FUNCTIONAL BLOCK DIAGRAM

ANALOG

ANALOG SUPPLY

DIGITAL SUPPLY

CLOCK SOURCE

POWER DOWN

RESET

DIGITAL

L_MIC

0 dB/

VARIABLE SAMPLE

AD1845

R_MIC

PLAYBACK REQ

20 dB

FREQUENCY GENERATOR

L_LINE

M

L

SD A/D

PLAYBACK ACK

R_LINE

GAIN

CONVERTER

m-LAW

L_AUX1

U

CAPTURE REQ

X

A-LAW

FIFO

R

SD A/D

R_AUX1

LINEAR

CAPTURE ACK

GAIN

P

CONVERTER

A

ADR1:0

R

A

DATA7:0

GAM

GAM

GAM

GAM = GAIN

DIGITAL MIX

L

L

CS

ATTENTUATE

ATTENUATE

E

MUTE

L

RD

L

ATTENUATE

SD D/A

L_OUT

S

S

S

S

P

MUTE

CONVERTER

WR

m-LAW

O

M_OUT

MUTE

S

A-LAW

FIFO

R

BUS DRIVER

T

R

LINEAR

CONTROL

ATTENUATE

SD D/A

R_OUT

S

S

S

S

HOST DMA

MUTE

CONVERTER

INTERRUPT

M_IN

GAM

GAM

EXTERNAL

CONTROL

L_AUX2

REFERENCE

R_AUX2

CONTROL

REGISTERS

VREF_F

VREF

SoundPort is a registered trademark of Analog Devices, Inc.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1997

AD1845–SPECIFICATIONS

STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED

Temperature	25	°C
Digital Supply (VDD)	5.0	V
Analog Supply (VCC)	5.0	V
Word Rate (FS)	48	kHz
Input Signal	1008	Hz
Analog Output Passband	20 Hz to 20 kHz
ADC FFT Size	2048
DAC FFT Size	8192
VIH	5	V
VIL	0	V

ANALOG INPUT

DAC Test Conditions

Calibrated

0 dB Relative to Full Scale

16-Bit Linear Mode

10 kΩ Output Load

Mute Off, OL = 0

ADC Test Conditions

Calibrated

0 dB Gain

–1.0 dB Relative to Full Scale Line Input

16-Bit Linear Mode

	Min	Typ	Max	Units
Input Voltage (RMS Values Assume Sine Wave Input)
Line		1		V rms
	2.55	2.83	3.35	V p-p
MIC with +20 dB Gain (MGE = 1)		0.1		V rms
	0.255	0.283	0.335	V p-p
MIC with 0 dB Gain (MGE = 0)		1		V rms
	2.55	2.83	3.35	V p-p
Input Impedance*	10	17		kΩ
Input Capacitance		15		pF
PROGRAMMABLE GAIN AMPLIFIER–ADC
	Min	Typ	Max	Units
Step Size (All Steps Tested)
(0 dB to 22.5 dB)	0.7	1.5	1.9	dB
PGA Gain Range Span	21.5	22.5	23.5	dB
AUXILIARY LINE, MONO, AND MICROPHONE INPUT ANALOG GAIN/AMPLIFIERS/ATTENUATORS
	Min	Typ	Max	Units
Step Size : AUX1, AUX2, LINE, MIC (All Steps Tested)
(+12 dB to –30 dB)	1.25	1.5	1.75	dB
(–31.5 dB to –34.5 dB)	1	1.5	2.0	dB
Step Size: M_IN (All Steps Tested)
(0 dB to –39 dB)	2.5	3.0	3.6	dB
(–42 dB to –45 dB)	2.2	3.0	3.85	dB
Input Gain/Attenuation Range: AUX1, AUX2, LINE, MIC	45.0	46.5	49.0	dB
Input Gain/Attenuation Range: M_IN	42	45	49	dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
	Min		Max	Units
Passband	0		0.4 × FS	Hz
Passband Ripple	0.4 × FS		±0.1	dB
Transition Band			0.6 × FS	Hz
Stopband	0.6 × FS		∞	Hz
Stopband Rejection	74			dB
Group Delay			15/FS	μs
Group Delay Variation Over Passband			0.0

*Guaranteed, not tested.

–2–

REV. C

				AD1845
ANALOG-TO-DIGITAL CONVERTERS
	Min	Typ	Max		Units
Resolution		16			Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted)	73	81			dB
THD+N (Referenced to Full Scale)			0.025		%
		–76	–72		dB
Signal-to-Intermodulation Distortion		85			dB
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)		–90	–80		dB
Line to MIC (Input LINE, Ground and Select MIC, Read ADC)		–90	–80		dB
Line to AUX1		–90	–80		dB
Line to AUX2		–90	–80		dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)	–18.5		+10		%
Interchannel Gain Mismatch (Difference of Gain Errors)			±0.9		dB
ADC Offset Error			10		mV
DIGITAL-TO-ANALOG CONVERTERS
	Min	Typ	Max		Units
Resolution		16			Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted)	74	82			dB
THD+N (Referenced to Full Scale)			0.032		%
		–78	–70		dB
Signal-to-Intermodulation Distortion		90			dB
Gain Error (Full-Scale Span Relative to Nominal Output Voltage)	–14.5		+10		%
Interchannel Gain Mismatch (Difference of Gain Errors)			±0.6		dB
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)			–80		dB
Total Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz)*			–50		dB
Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)*			–70		dB
DAC ATTENUATOR
	Min	Typ	Max		Units
Step Size (0 dB to –22.5 dB)	1.3	1.5	1.7		dB
Step Size (–22.5 dB to –94.5 dB)*	1.0	1.5	2.0		dB
Output Attenuation Range Span*	93.5	94.5	95.5		dB
ANALOG OUTPUT
	Min	Typ	Max		Units
Full-Scale Output Voltage
OL = 0	1.7	2.0	2.2		V p-p
OL = 1	2.4	2.83	3.11		V p-p
Output Impedance*			600		Ω
External Load Impedance	10				kΩ
Output Capacitance*			15		pF
External Load Capacitance			100		pF
VREF	2.05	2.25	2.60		V
VREF Current Drive		100			μA
VREF Output Impedance		4			kΩ
Mute Attenuation of 0 dB Fundamental* (L_OUT, R_OUT, M_OUT)			–80		dB
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*			±5		mV

*Guaranteed, not tested.

REV. C

–3–

AD1845

SYSTEM SPECIFICATIONS

Min Typ

Max

Units

System Frequency Response Ripple (Line In to Line Out)*

1.0

dB

Differential Nonlinearity*

±1

LSB

Phase Linearity Deviation*

5

Degrees

STATIC DIGITAL SPECIFICATIONS

Min

Max

Units

High Level Input Voltage (VIH)

Digital Inputs

2.4

V

XTAL1I

2.4

V

Low Level Input Voltage (VIL)

0.8

V

High Level Output Voltage (VOH) IOH = –2 mA

2.4

V

Low Level Output Voltage (VOL) IOL = 2 mA

0.4

V

Input Leakage Current

–10

10

μA

Output Leakage Current

–10

10

μA

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, VDD = VCC = 5.0 V)

Min

Max

Units

/

Strobe Width

(tSTW)

100

ns

WR

RD

WR

/

RD

Rising to

WR

/

RD

Falling

(tBWND)

80

ns

Write Data Setup to WR Rising

(tWDSU)

10

ns

RD

Falling to Valid Read Data

(tRDDV)

40

ns

CS

Setup to

WR

/

RD

Falling

(tCSSU)

10

ns

CS Hold from WR/

RD

Rising

(tCSHD)

0

ns

Adr Setup to

WR

/

RD

Falling

(tADSU)

10

ns

Adr Hold from

WR

/

RD

Rising

(tADHD)

10

ns

DAK Rising to WR/RD Falling

(tSUDK1)

20

ns

DAK

Falling to

WR

/

RD

Rising

(tSUDK2)

0

ns

DAK

Setup to

WR

/

RD

Falling

(tDKSU)

10

ns

Data Hold from RD Rising

(tDHD1)

20

ns

Data Hold from

WR

Rising

(tDHD2)

15

ns

DRQ Hold from

WR

/

RD

Falling

(tDRHD)

25

ns

DAK Hold from WR Rising

(tDKHDa)

10

ns

DAK

Hold from

RD

Rising

(tDKHDb)

10

ns

DBEN

/DBDIR Delay from

WR

/

RD

Falling

(tDBDL)

30

ns

PWRDWN and RESET Low Pulsewidth

300

ns

*Guaranteed, not tested.

–4–

REV. C

				AD1845
POWER SUPPLY
	Min	Typ	Max		Units
Power Supply Range–Digital and Analog	4.75		5.25		V
Power Supply Current			130		mA
Analog Supply Current			45		mA
Digital Supply Current			85		mA
Power Dissipation
(Current × Nominal Supplies)			650		mW
Power-Down Supply Current			2		mA
Reset Supply Current		2			mA
Total Power-Down Supply Current			30		mA
Standby Supply Current		36			mA
Mixer Power-Down Supply Current			70		mA
Mixer Only Supply Current		52			mA
ADC Power-Down Supply Current			80		mA
DAC Power-Down Supply Current			85		mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, both ADCs and DACs)	40				dB
CLOCK SPECIFICATIONS*
		Min	Max		Units
Input Clock Frequency			33		MHz
Recommended Clock Duty Cycle		10	90		%
Power Up Initialization Time			512		ms

*Guaranteed, not tested.

Specifications subject to change without notice.

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option1
AD1845JP	0°C to +70°C	68-Lead PLCC	P-68A
AD1845JP-REEL2	0°C to +70°C	68-Lead PLCC	P-68A
AD1845JST	0°C to +70°C	100-Lead TQFP	ST-100

NOTES

1P = Plastic Leaded Chip Carrier; ST = Thin Quad Flatpack. 213" Reel, multiples of 250 pcs.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

TAMB = TCASE – (PD × θCA)

TCASE = Case Temperature in °C

PD = Power Dissipation in W

θCA = Thermal Resistance (Case-to-Ambient)

θJA = Thermal Resistance (Junction-to-Ambient)

θJC = Thermal Resistance (Junction-to-Case)

Package	uJA	uJC	uCA
PLCC	38°C/W	8°C/W	30°C/W
TQFP	44°C/W	8°C/W	93°C/W

ABSOLUTE MAXIMUM RATINGS*

	Min	Max	Units
Power Supplies
Digital (VDD)	–0.3	6.0	V
Analog (VCC)	–0.3	6.0	V
Input Current		±10.0
(Except Supply Pins)			mA
Analog Input Voltage (Signal Pins)	–0.3	VCC +0.3	V
Digital Input Voltage (Signal Pins)	–0.3	VDD +0.3	V
Ambient Temperature (Operating)	0	+70	°C
Storage Temperature	–65	+150	°C

*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–5–

AD1845

68-Lead PLCC

PIN DESIGNATIONS

							ADR1	GNDD		V		DATA0		DATA1		DATA2			DATA3		GNDD			V			DATA4			DATA5			DATA6			DATA7			GNDD				DBEN			DBDIR			WR
											DD														DD
						9		8		7		6		5		4			3		2			1			68			67			66			65			64				63			62			61
	ADR0																																																60			RD
			10
																																																	59			CS
	CDAK		11
	CDRQ		12																																														58			XCTL1
																																																	57			INT
	PDAK		13
	PDRQ		14																																														56			XCTL0
	VDD		15																																														55			NC
	GNDD		16																	AD1845																													54			VDD
XTAL1I			17																	TOP VIEW																													53			GNDD
																			(Not to Scale)
XTAL1O			18																																														52			NC
	VDD		19																																														51			NC
	GNDD		20																																														50			NC
XTAL2I			21																																														49			NC
XTAL2O			22																																														48			NC
			23																																														47			M_OUT
PWRDWN
			24																																														46			M_IN
RESET
	GNDD		25																																														45			VDD
R_FILT			26		27		28		29		30		31		32		33			34		35			36			37			38			39			40			41				42			43		44			GNDD
					_LINER		_RMIC		_LMIC		_LINEL		_FILTL		V		V			GNDA		V			V			GNDA			_AUX2L			_AUX1L			_OUTL			_OUTR				_AUX1R			_AUX2R
															REF		REFF_						CC			CC

NC = NO CONNECT

											ADR1				GNDD				V				NC				NC				NC			NC			DATA0			DATA1				DATA2			DATA3				GNDD			V			DATA4				DATA5			DATA6			DATA7			NC			NC			NC			NC			GNDD				DBEN			DBDIR				WR
																				DD																																		DD
											100				99				98				97				96				95			94			93			92				91			90				89			88			87				86			85			84			83			82			81			80			79			78				77				76
																																																																																												75					RD
			ADR0					1
																																																																																												74					CS
				NC				2																																																																																									XCTL1
																																																																																												73
				NC
								3																																																																																									INT
																																																																																												72
				NC
								4																																																																																									XCTL0
																																																																																												71
				NC
								5																																																																																									NC
																																																																																												70
		CDAK						6																																																																																									NC
																																																																																												69
		CDRQ
								7																																																																																									VDD
																																																																																												68
		PDAK						8																																																																																									GNDD
																																																																																												67
		PDRQ						9																																																																																									NC
																																																																																												66
				VDD				10																																																																																									NC
																																																																																												65
		GNDD						11																																									AD1845																																																NC
100-Lead TQFP																																																																																												64
	XTAL1I							12																																																																																									NC
																																																	TOP VIEW																																											63
	XTAL1O							13																																							(Not to Scale)																																																	62	NC
				VDD				14																																																																																									NC
																																																																																												61
		GNDD						15																																																																																									NC
																																																																																												60
	XTAL2I							16																																																																																									NC
																																																																																												59
	XTAL2O							17																																																																																									NC
																																																																																																58
	PWRDWN							18																																																																																									M_OUT
																																																																																																57
	RESET							19																																																																																									M_IN
																																																																																												56
		GNDD						20																																																																																									VDD
																																																																																												55
				NC				21
																																																																																												54					GNDD
				NC				22
																																																																																												53					NC
				NC				23
																																																																																												52					NC
				NC				24
																																																																																												51					NC
	R_FILT							25					27				28				29				30				31			32			33			34			35				36				37			38			39				40				41				42			43			44			45			46			47		48				49				50
										26
										NC			NC				LINER				RMIC				LMIC				LINEL			NC			FILTL			NC			V				NC				NC			V			NC				GNDA				V				V			GNDA			AUX2L			AUX1L			OUTL			OUTR			AUX1R				AUX2R			NC
																																										REF											REFF											CC			CC

NC = NO CONNECT

–6–

REV. C

AD1845

PIN FUNCTION DESCRIPTIONS

Parallel Interface

Pin Name

PLCC

TQFP

I/O

Description

CDRQ

12

7

O

Capture Data Request. The assertion of this signal HI indicates that the codec has a cap-

tured audio sample from the ADC ready for transfer. This signal will remain asserted

until the internal capture FIFO is empty.

11

6

I

Capture Data Acknowledge. The assertion of this active LO signal indicates that the

CDAK

RD

cycle occurring is a DMA read from the capture buffer.

PDRQ

14

9

O

Playback Data Request. The assertion of this signal HI indicates that the codec is ready

for more DAC playback data. The signal will remain asserted until the internal playback

FIFO is full.

13

8

I

Playback Data Acknowledge. The assertion of this active LO signal indicates that the

PDAK

WR

cycle occurring is a DMA write to the playback buffer.

ADR1:0

9 & 10

100 & 1

I

Codec Addresses. These address pins are asserted by the codec interface logic during a

control register/PIO access. The state of these address lines determine which direct

register is accessed.

60

75

I

Read Command Strobe. This active LO signal defines a read cycle from the codec. The

RD

cycle may be a read from the control/PIO registers, or the cycles could be a read from

the codec’s DMA sample registers.

61

76

I

Write Command Strobe. This active LO signal indicates a write cycle to the codec. The

WR

cycle may be a write to the control/PIO registers, or the cycle could be a write to the

codec’s DMA sample registers.

59

74

I

AD1845 Chip Select. The codec will not respond to any control/PIO cycle accesses

CS

unless this active LO signal is LO. This signal is ignored during DMA transfers.

DATA7:0

3–6 &

84–87 &

I/O

Data Bus. These pins transfer data and control information between the codec and

65–68

90–93

the host.

63

78

O

Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.

DBEN

For control register/PIO cycles,

DBEN = (

WR

or RD) and CS

For DMA cycles,

DBEN

= (

WR

or

RD

) and (

PDAK

or

CDAK

).

DBDIR

62

77

O

Data Bus Direction. This pin controls the direction of the data bus transceiver. HI

enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to

the host bus. This signal is normally HI.

For control register/PIO cycles,

DBDIR =

RD

and CS

For DMA cycles,

DBDIR =

RD

and (

PDAK

or

CDAK

).

REV. C

–7–

AD1845

Analog Signals

Pin Name					PLCC	TQFP	I/O	Description
L_LINE					30	31	I	Left Line Input.
R_LINE					27	28	I	Right Line Input.
L_MIC					29	30	I	Left Microphone Input. This signal can be either line level or –20 dB from line level
								(using the on-chip 20 dB gain block).
R_MIC					28	29	I	Right Microphone Input. This signal can be either line level or –20 dB from line level
								(using the on-chip 20 dB gain block).
L_AUX1					39	45	I	Left Auxiliary #1 Line Input.
R_AUX1					42	48	I	Right Auxiliary #1 Line Input.
L_AUX2					38	44	I	Left Auxiliary #2 Line Input.
R_AUX2					43	49	I	Right Auxiliary #2 Line Input.
L_OUT					40	46	O	Left Line Output.
R_OUT					41	47	O	Right Line Output.
M_IN					46	56	I	Mono Input.
M_OUT					47	57	O	Mono Output.
Miscellaneous
Pin Name					PLCC	TQFP	I/O	Description
XTAL1I					17	12	I	24.576 MHz Crystal #1 Input.
XTAL1O					18	13	O	24.576 MHz Crystal #1 Output.
XTAL2I					21	16		Not used on the AD1845.
XTAL2O					22	17		Not used on the AD1845.
					23	18	I	Power Down Signal. Active LO places the AD1845 in its lowest power consumption
PWRDWN
								mode. All sections of the AD1845, including the digital interface, are shut down and
								consume minimal power.
INT					57	72	O	Host Interrupt Pin. A host interrupt is generated to notify the host that a specified
								event has occurred.
XCTL1:0					58 & 56	73 & 71	O	External Control. These signals reflect the current status of register bits inside the
								AD1845. They can be used for signaling or to control external logic.
					24	19	I	Reset. Active LO resets all digital registers and filters, and resets all analog filters. Active
RESET
								LO places the AD1845 in the lowest power consumption mode. XTAL1 is required to be
								running during the minimum low pulsewidth of the reset signal.
VREF					32	35	O	Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-
								shifting. VREF should not be used to sink or source current.
VREF_F					33	38	I	Voltage Reference Filter. Voltage reference filter point for external bypassing only.
L_FILT					31	33	I	Left Channel Filter. This pin requires a 1.0 μF capacitor to analog ground for proper
								operation.
R_FILT					26	25	I	Right Channel Filter. This pin requires a 1.0 μF capacitor to analog ground for proper
								operation.
NC					48–52,	2–5, 21–24		No Connect.
					55	26, 27, 32, 34,
						36, 37, 39,
						50–53, 58–66,
						69, 70, 80–83,
						94–97

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AD1845

Power Supplies

Pin Name	PLCC	TQFP	I/O	Description
VCC	35 & 36	41 & 42	I	Analog Supply Voltage (+5 V).
GNDA	34 & 37	40 & 43	I	Analog Ground.
VDD	1, 7, 15,	10, 14,	I	Digital Supply Voltage (+5 V).
	19, 45,	55, 68,
	54	88, 98
GNDD	2, 8, 16,	11, 15, 20,	I	Digital Ground.
	20, 25,	54, 67,
	44, 53,	79, 89,
	64	99

(Continued from page 1)

AD1845	ADDRESS		18	AEN
CS	DECODE			SA19:2
A1				SA1
A0				SA0
WR				IOWC	I
RD				IORC
					S
8	74_245		8		A
				DATA7:0
DATA7:0
DBDIR	DIR				B
DBEN	G				U
					S
B		A
PDRQ				DRQ <X>
CDRQ				DRQ <Y>
PDAK				DAK <X>
CDAK				DAK <Y>
INT				IRQ <Z>

Figure 1. Interface to ISA Bus

External circuit requirements are limited to a minimal number of low cost support components. Anti-imaging DAC output filters are incorporated on-chip. Dynamic range exceeds 80 dB over the 20 kHz audio band. Sample rates from 4 kHz to 50 kHz are supported from a single external crystal or clock source.

The AD1845 has built-in 8/16 mA (user selectable) bus drivers. If 24 mA drive capability is required, the AD1845 generates enable and direction controls for IC bus buffers such as the

74 245.

The codec includes a stereo pair of åD analog-to-digital converters and a stereo pair of åD digital-to-analog converters. The AD1845 mixer surpasses MPC Level-2 recommendations. Inputs to the ADC can be selected from four stereo pairs of analog signals: line (LINE), microphone (MIC), auxiliary line #1 (AUX1), and post-mixed DAC output. A software-con- trolled programmable gain stage allows independent gain for each channel going into the ADC. In addition, the analog mixer allows the mono input (M_IN), MIC, AUX1, LINE and auxiliary line #2 (AUX2) signals to be mixed with the DACs’ output. The ADCs’ output can be digitally mixed with the DACs’ input.

The pair of 16-bit outputs from the ADCs is available over a byte-wide bidirectional interface that also supports 16-bit digital input to the DACs and control information. The AD1845 can accept and generate 16-bit twos complement PCM linear digital data in both little endian or big endian byte ordering, 8-bit

unsigned magnitude PCM linear data, and 8-bit m-law or A-law companded digital data.

The åD DACs are preceded by a digital interpolation filter. An attenuator provides independent user volume control over each DAC channel. Nyquist images and shaped quantized noise are removed from the DACs’ analog stereo output by on-chip switched-capacitor and continuous-time filters.

The AD1845 supports multiple low power and power-down modes to support notebook and portable computing multimedia applications. The ADC, DAC, and mixer paths can be suspended independently allowing the AD1845 to be used for capture-only or playback-only, lessening power consumption and extending battery life.

The AD1845 includes a variable sample frequency generator, that allows the codec to instantaneously change sample rates with a resolution of 1 Hz without “clicks” and “pops.” Additionally, åD quantization noise is kept out of the 20 kHz audio band regardless of the chosen sample rate. The codec uses the variable sample frequency generator to derive all internal clocks from a single external crystal or clock source.

Expanded Mode (MODE2)

MODE1 is the initial state of the AD1845. In this state the AD1845 appears as an AD1848 compatible device. To access the expanded modes of operation on the AD1845, the MODE2 bit should be set in the Miscellaneous Information Control Register. When this bit is set to one, 16 additional indirect registers can be addressed allowing the user to access the AD1845’s expanded features. The AD1845 can return to MODE1 operation by clearing the MODE2 bit. In both MODE1 and MODE2, the capture and playback FIFOs are active to prevent data loss.

The additional MODE2 functions are:

1.Full-Duplex DMA support.

2.MIC input mixer, mute and volume control.

3.Mono output with mute control.

4.Mono input with mixer volume control.

5.Software controlled advanced power-down modes.

6.Programmable sample rates from 4 kHz to 50 kHz in 1 Hz increments.

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AD1845

FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1845 and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. The user is not expected to refer repeatedly to this section.

Analog Inputs

The AD1845 SoundPort Stereo Codec accepts stereo line-level and microphone-level inputs. The LINE, MIC, AUX1, and post-mixed DAC output are available to the ADC multiplexer. The DAC output can be mixed with LINE, MIC, AUX1, AUX2 and M_IN. Each channel of the MIC inputs can be amplified by +20 dB to compensate for the difference between line levels and typical condenser microphone levels.

Analog Mixing

The M_IN mono input signal, MIC, LINE, AUX1 and AUX2 analog stereo signals can be mixed in the analog domain with the DAC output. Each channel of each AUX, LINE and MIC analog input can be independently gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps or completely muted. M_IN can be attenuated from 0 dB to –45 dB in 3 dB steps or muted. The post-mixed DAC outputs are available on L_OUT and R_OUT and also to the ADC input multiplexer.

Even if the AD1845 is not playing back data from its DACs, the analog mix function can still be active.

Analog-to-Digital Datapath

The PGA following the input multiplexer allows independent selectable gains for each channel from 0 dB to 22.5 dB in +1.5 dB steps. The codec can operate either in a global stereo mode or in a global mono mode with left-channel inputs appearing at both channel outputs.

The AD1845 åD ADCs incorporate a fourth-order modulator. A single pole of passive filtering is all that is required for antialiasing the analog input because of the ADC’s high over sampling ratio. The ADCs include linear-phase digital decimation filters that low-pass filter the input to 0.4 ´ FS. (“FS” is the word rate or “sampling frequency.”) ADC input over range conditions are reported on status bits in the Test and Initialization Register.

Digital-to-Analog Datapath

The åD DACs are preceded by a programmable attenuator and a low-pass digital interpolation filter. The anti-imaging interpolation filter over samples and digitally filters the higher frequency images. The attenuator allows independent control of each DAC channel from 0 dB to –94.5 dB in –1.5 dB steps plus full mute. The DACs’ åD noise shapers also over sample and convert the signal to a single-bit stream. The DAC outputs are then filtered in the analog domain by a combination of switchedcapacitor and continuous-time filters. They remove the very high frequency components of the DAC bit stream output. No external components are required.

Changes in DAC output attenuation take effect only on zero crossings, eliminating “zipper” noise on playback. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of a zero crossing. The time-out period is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds at an 8 kHz sampling rate. (Timeout [ms] » 384 ¸ FS [kHz].)

Digital Mixing

Stereo digital output from the ADCs can be digitally mixed with the input to the DACs. Digital output from the ADCs going out of the data port is unaffected by the digital mix. Along the digital mix datapath, the 16-bit linear output from the ADCs is attenuated by an amount specified with control bits. Both channels of the digital mix datapath are attenuated by the same amount. (Note that internally the AD1845 always works with 16-bit PCM linear data, digital mixing included; format conversions take place at the input and output.)

Sixty-four steps of –1.5 dB attenuation are supported to –94.5 dB. The digital mix datapath can also be completely muted. Note that the level of the mixed signal is also a function of the input PGA settings, since they affect the ADCs’ output.

The attenuated digital mix data is digitally summed with the DAC input data prior to the DACs’ datapath attenuators. The digital sum of digital mix data and DAC input data is clipped at plus or minus full scale and does not wrap around. Because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the DACs’ datapath attenuators.

In case the AD1845 is capturing data, but ADC output data is not removed in time (“ADC overrun”), the last sample captured before overrun will be used for the digital mix. In case the AD1845 is playing back data, but input digital DAC data fails to arrive in time (“DAC underrun”), a midscale zero will be added to the digital mix data when the DACZ control bit is set to 0; otherwise, the DAC will output the previous valid sample in an underrun condition.

Analog Outputs

Stereo and mono line-level outputs are available at external pins. Each channel of this output can be independently muted. When muted, the outputs will settle to a dc value near VREF, the midscale reference voltage. The output is selectable for 2.0 V peak-to-peak or 2.8 V peak-to-peak. When selecting the LINE output as an input to the ADC, the ADC automatically compensates for the output level selection.

Digital Data Types

The AD1845 supports five global data types: 16-bit twos complement linear PCM (little endian and big endian byte ordering), 8-bit unsigned linear PCM, companded m-law, and 8-bit companded A-law, as specified by control register bits. Data in all formats is always transferred MSB first. All data formats that are less than 16 bits are MSB-aligned to ensure the use of full system resolution.

The 16-bit PCM data format is capable of representing 96 dB of dynamic range. Eight-bit PCM can represent 48 dB of dynamic range. Companded m-law and A-law data formats use nonlinear coding with less precision for large amplitude signals. The loss of precision is compensated for by an increase in dynamic range to 64 dB and 72 dB, respectively.

On input, 8-bit companded data is expanded to an internal linear representation, according to whether m-law or A-law was specified in the codec’s internal registers. Note that when m-law compressed data is expanded to a linear format, it requires 14 bits. A-law data expanded requires 13 bits.

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AD1845

COMPRESSED	15		8	7		0
		MSB	LSB
INPUT DATA
						0
	15			3/2	2/1
EXPANSION		MSB		LSB
						0
	15			3/2	2/1
DAC INPUT		MSB		LSB	0 0 0 / 0 0

Figure 2. μ-Law or A-Law Expansion

When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified.

	15					0
ADC OUTPUT		MSB				LSB
	15			3/2	2/1	0
TRUNCATION		MSB		LSB
						0
	15		8	7
COMPRESSION		MSB	LSB	0 0 0 0 0 0 0 0

Figure 3. μ-Law or A-Law Compression

Note that all format conversions take place at input or output. Internally, the AD1845 always uses 16-bit linear PCM representations to maintain maximum precision.

Timer Registers

The timer registers are provided for system level synchronization, and for periodic interrupt generation. The 16-bit timer time base is determined by the frequency of the connected input clock source.

The timer is enabled by setting the Timer Enable bit, TE, in the Alternate Feature Enable register. To set the timer, load the Upper and Lower Timer Bits Registers. The timer value will then be loaded into an internal count register with a value of approximately 10 μs (the exact timer value is listed in the register descriptions). The internal count register will decrement until it reaches zero, then the Timer Interrupt bit, TI, is set and an interrupt will be sent to the host. The next timer clock will load the internal count register with the value of the Timer Register, and the timer will be reinitialized. To clear the interrupt, write to the Status Register or write a “0” to TI.

Interrupts

The AD1845 supports interrupt conditions generated by DMA playback count expiration, DMA capture count expiration, or timer expiration. The INT bit will remain set, HI, until a write has been completed to the Status Register or by clearing the TI, CI, or PI bit (depending on the existing condition) in the Capture Playback Timer Register. The IEN bit of the Pin Control Register determines whether the interrupt pin responds to an interrupt condition and reflects the interrupt state on the INT status bit.

Power Supplies and Voltage Reference

The AD1845 operates from a +5 V power supply. Independent analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single-supply systems. A voltage reference is included on the codec and its 2.25 V buffered output is available on an external pin (VREF). The reference output can be used for biasing op amps used in dc coupling. The internal reference is externally bypassed to analog ground at the VREF_F pin.

Clocks and Sample Rates

The AD1845 operates from a single external crystal or clock source. From a single input, a wide range of sample rates can be generated. The AD1845 default frequency source is a

24.576 MHz input. The AD1845 can also be driven from a 14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input frequency source. In MODE1, the input drives the internal variable sample frequency generator to derive the following AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,

48 kHz. In MODE2, the AD1845 can be programmed to generate any sample frequency between 4 kHz and 50 kHz with

1 Hz resolution. Note that it is no longer required to enter Mode Change Enable (MCE) to change the sample rate. This feature allows the user to change the AD1845’s sample rate “on the fly.”

CONTROL REGISTERS Control Register Architecture

The AD1845 SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 37 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on whether the transfer is for a playback or capture.)

ADR1:0	Register Name
0	Index Address Register
1	Indexed Data Register
2	Status Register
3	PIO Data Register

Figure 4. Direct Register Map

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AD1845

A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without indexing. The 32 Indirect Register indexes are shown in Figure 5:

Index	Register Name	Reset/Default State
0	Left Input Control	000x	0000
1	Right Input Control	000x	0000
2	Left Aux #1 Input Control	1xx0	1000
3	Right Aux #1 Input Control	1xx0	1000
4	Left Aux #2 Input Control	1xx0	1000
5	Right Aux #2 Input Control	1xx0	1000
6	Left Output Control	1x00	0000
7	Right Output Control	1x00	0000
8	Clock and Data Format	0000	0000
9	Interface Configuration	00xx	1000
10	Pin Control	00xx	xx00
11	Test and Initialization	0000	0000
12	Miscellaneous Information	10x0	1010
13	Digital Mix/Attenuation	0000	00x0
14	Upper Base Count	0000	0000
15	Lower Base Count	0000	0000
16	Alternate Feature Enable/Left MIC Input Control	0001	0001
17	MIC Mix Enable/Right MIC Input Control	0001	000x
18	Left Line Gain, Attenuate, Mute, Mix	1xx0	1000
19	Right Line Gain, Attenuate, Mute, Mix	1xx0	1000
20	Lower Timer	0000	0000
21	Upper Timer	0000	0000
22	Upper Frequency Select	0001	1111
23	Lower Frequency Select	0100	0000
24	Capture Playback Timer	x000	0000
25	Revision ID	100x	x000
26	Mono Control	00xx	0011
27	Power-Down Control	000x	0xxx
28	Capture Data Format Control	0000	xxxx
29	Crystal Clock Select/Total Power-Down	000x	xxx0
30	Capture Upper Base Count	0000	0000
31	Capture Lower Base Count	0000	0000

“x” indicates reserved bit, always write “0s” to these bits.

Figure 5. Indirect Register Map and Reset/Default States

A detailed map of all direct and indirect register contents is summarized for reference as follows:

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