Fairchild Semiconductor 74ACT377SJX, 74ACT377SJ, 74ACT377SCX, 74ACT377SC, 74ACT377PC Datasheet

November 1988

Revised November 1999

74AC377 • 74ACT377

Octal D-Type Flip-Flop with Clock Enable

General Description

The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features

■ICC reduced by 50%

■Ideal for addressable register applications

■Clock enable for address and data synchronization applications

■Eight edge-triggered D-type flip-flops

■Buffered common clock

■Outputs source/sink 24 mA

■See 273 for master reset version

■See 373 for transparent latch version

■See 374 for 3-STATE version

■ACT377 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74AC377SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC377SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC377PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT377SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT377SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT377PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
			Pin Names		Description
			D0–D7		Data Inputs
					Clock Enable (Active LOW)
			CE
			Q0–Q7		Data Outputs
			CP		Clock Pulse Input

FACT is a trademark of Fairchild Semiconductor Corporation.

Enable Clock with Flop-Flip Type-D Octal 74ACT377 • 74AC377

© 1999 Fairchild Semiconductor Corporation

DS009961

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74AC377 • 74ACT377

Logic Symbols

IEEE/IEC

Mode Select-Function Table

Operating Mode		Inputs				Outputs
					Dn	Qn
	CP		CE
Load ‘1'			L		H	H
Load ‘0'			L		L	L
Hold (Do Nothing)			H		X	No Change
	X		H		X	No Change

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V	− 20 mA
VI =	VCC + 0.5V	+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V	− 20 mA
VO =	VCC + 0.5V	+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		± 50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
Junction Temperature (TJ)
PDIP		140° C

Recommended Operating

Conditions

Supply Voltage (VCC)
AC	2.0V to 6.0V
ACT	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V	125 mV/ns
Minimum Input Edge Rate (∆ V/∆ t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics for AC

Symbol	Parameter	VCC	TA = + 25° C			TA = − 40° C to + 85° C	Units		Conditions
		(V)	Typ		Guaranteed Limits
VIH	Minimum HIGH Level	3.0	1.5	2.1		2.1		VOUT =		0.1V
	Input Voltage	4.5	2.25	3.15		3.15	V	or VCC −			0.1V
		5.5	2.75	3.85		3.85
VIL	Maximum LOW Level	3.0	1.5	0.9		0.9		VOUT =		0.1V
	Input Voltage	4.5	2.25	1.35		1.35	V	or VCC −			0.1V
		5.5	2.75	1.65		1.65
VOH	Minimum HIGH Level	3.0	2.99	2.9		2.9
	Output Voltage	4.5	4.49	4.4		4.4	V	IOUT =		−	50 µ A
		5.5	5.49	5.4		5.4
								VIN =	VIL or VIH
		3.0		2.56		2.46		IOH =	−	12 mA
		4.5		3.86		3.76	V	IOH =	−	24 mA
		5.5		4.86		4.76		IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	3.0	0.002	0.1		0.1
	Output Voltage	4.5	0.001	0.1		0.1	V	IOUT =		50 µ A
		5.5	0.001	0.1		0.1
								VIN =	VIL or VIH
		3.0		0.36		0.44		IOL =	12 mA
		4.5		0.36		0.44	V	IOL =	24 mA
		5.5		0.36		0.44		IOL =	24 mA (Note 2)
IIN	Maximum Input	5.5		± 0.1		± 1.0	µ A	VI =	VCC,
(Note 4)	Leakage Current							GND
IOLD	Minimum Dynamic	5.5				75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 3)	5.5				− 75	mA	VOHD =			3.85V Min
ICC	Maximum Quiescent	5.5		4.0		40.0	µ A	VIN =	VCC or GND
(Note 4)	Supply Current

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

74ACT377 • 74AC377

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