Fairchild Semiconductor 74ACT253SCX, 74ACT253SC, 74ACT253PC, 74ACT253MTCX, 74ACT253MTC Datasheet
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November 1988
Revised November 1999
74AC253 • 74ACT253
Dual 4-Input Multiplexer with 3-STATE Outputs
General Description
The AC/ACT253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems.
Features
■ICC and IOZ reduced by 50%
■Multifunction capability
■Noninverting 3-STATE outputs
■Outputs source/sink 24 mA
■ACT253 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC253SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74AC253SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC253PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT253SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74ACT253SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACT253PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagrams |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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I0a–I3a |
Side A Data Inputs |
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I0b–I3b |
Side B Data Inputs |
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S0, S1 |
Common Select Inputs |
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Side A Output Enable Input |
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OE |
a |
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Side B Output Enable Input |
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OE |
b |
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Za, Zb |
3-STATE Outputs |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Multiplexer Input-4 Dual 74ACT253 • 74AC253
© 1999 Fairchild Semiconductor Corporation |
DS009946 |
www.fairchildsemi.com |
74AC253 • 74ACT253
Functional Description
The AC/ACT253 contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-
input multiplexers have individual Output Enable (OEa,
OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown:
Za = OEa • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0)
Zb = OEb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0)
If the outputs of 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3- STATE devices whose outputs are tied together are designed so that there is no overlap.
Logic Diagram
Truth Table
Select |
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Data Inputs |
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Output |
Outputs |
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Inputs |
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Enable |
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S0 |
S1 |
I0 |
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I1 |
I2 |
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I3 |
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OE |
Z |
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X |
X |
X |
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X |
X |
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X |
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H |
Z |
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L |
L |
L |
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X |
X |
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X |
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L |
L |
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L |
L |
H |
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X |
X |
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X |
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L |
H |
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H |
L |
X |
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L |
X |
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X |
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L |
L |
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H |
L |
X |
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H |
X |
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X |
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L |
H |
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L |
H |
X |
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X |
L |
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X |
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L |
L |
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L |
H |
X |
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X |
H |
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X |
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L |
H |
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H |
H |
X |
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X |
X |
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L |
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L |
L |
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H |
H |
X |
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X |
X |
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H |
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L |
H |
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Address Inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± |
50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± |
50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
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TA = + 25° C |
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TA = − 40° C to + 85° C |
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Symbol |
Parameter |
CC |
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Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
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2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
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0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
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2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
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4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
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5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
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0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
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0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
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0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN (Note 4) |
Maximum Input Leakage Current |
5.5 |
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± |
0.1 |
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± |
1.0 |
µ A |
VI = |
VCC, GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Current |
5.5 |
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± |
0.25 |
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± |
2.5 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC (Note 4) |
Maximum Quiescent Supply Current |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT253 • 74AC253
3 |
www.fairchildsemi.com |
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