Fairchild Semiconductor 74ACT299SCX, 74ACT299SC, 74ACT299PC, 74ACT299MTCX, 74ACT299MTC Datasheet
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July 1988
Revised November 1999
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
General Description
The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
Features
■ICC and IOZ reduced by 50%
■Common parallel I/O for reduced pin count
■Additional serial inputs and outputs for expansion
■Four operating modes: shift left, shift right, load and store
■3-STATE outputs for bus-oriented applications
■Outputs source/sink 24 mA
■ACT299 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC299SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74AC299SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC299MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74AC299PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT299SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACT299MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT299PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
Description |
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CP |
Clock Pulse Input |
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DS0 |
Serial Data Input for Right Shift |
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DS7 |
Serial Data Input for Left Shift |
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S0, S1 |
Mode Select Inputs |
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Asynchronous Master Reset |
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MR |
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2 |
3-STATE Output Enable Inputs |
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OE |
1, |
OE |
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I/O0–I/O7 |
Parallel Data Inputs or |
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3-STATE Parallel Outputs |
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Q0, Q7 |
Serial Outputs |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Register Shift/Storage Universal Input-8 74ACT299 • 74AC299
© 1999 Fairchild Semiconductor Corporation |
DS009893 |
www.fairchildsemi.com |
74AC299 • 74ACT299
Logic Symbols
IEEE/IEC
Truth Table
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Inputs |
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Response |
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MR |
S1 |
S0 |
CP |
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L |
X |
X |
X |
Asynchronous Reset; Q0–Q7 = LOW |
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H |
H |
H |
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Parallel Load; I/On → Qn |
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H |
L |
H |
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Shift Right; DS0 → |
Q0, Q0 → |
Q1, etc. |
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H |
H |
L |
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Shift Left, DS7 → |
Q7, Q7 → |
Q6, etc. |
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H |
L |
L |
X |
Hold |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
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2 |
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT299 • 74AC299
3 |
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74AC299 • 74ACT299
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source or Sink Current (IO) |
± |
50 mA |
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DC VCC or Ground Current |
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Per Output Pin (ICC or IGND) |
± |
50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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(PDIP) |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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(Unless Otherwise Specified) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.0V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
TA = 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
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− |
50 µ A |
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5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
V |
IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
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IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
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50 µ A |
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5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOH = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOH = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOH = |
24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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± 0.1 |
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± 1.0 |
µ A |
VI = VCC, GND |
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(Note 4) |
Leakage Current |
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IOLD |
Minimum Dynamic |
5.5 |
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86 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC (Note 4) |
Maximum Quiescent |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC or GND |
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Supply Current |
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