Fairchild Semiconductor 74ACT175CW, 74ACT175SJX, 74ACT175SJ, 74ACT175SCX, 74ACT175SC Datasheet

November 1988

Revised November 1999

74AC175 • 74ACT175 Quad D-Type Flip-Flop

General Description

The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.

Features

■ICC reduced by 50%

■Edge-triggered D-type inputs

■Buffered positive edge-triggered clock

■Asynchronous common reset

■True and complement output

■Outputs source/sink 24 mA

■ACT175 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74AC175SC	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC175SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC	MTC16	16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT175SC	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT175SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC	MTC16	16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT175PC	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

		Pin Names					Description
		D0–D3					Data Inputs
		CP					Clock Pulse Input
							Master Reset Input
		MR
	Q0–Q3						True Outputs
	Q		0–Q			3	Complement Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.

Flop-Flip Type-D Quad 74ACT175 • 74AC175

© 1999 Fairchild Semiconductor Corporation

DS009936

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74AC175 • 74ACT175

Functional Description

The AC/ACT175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-

to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

Logic Diagram

Truth Table

Inputs					Outputs
@ tn,		= H
	MR				@ tn+ 1
Dn				Qn	Qn
	L			L		H
	H			H		L
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse

tn+ 1 = Bit Time after Clock Pulse

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V		− 20 mA
VI =	VCC + 0.5V		+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V		− 20 mA
VO =	VCC + 0.5V		+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		±	50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		±	50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
Junction Temperature (TJ)
PDIP			140° C

Recommended Operating

Conditions

Supply Voltage (VCC)
AC	2.0V to 6.0V
ACT	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V	125 mV/ns
Minimum Input Edge Rate (∆ V/∆ t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications

DC Electrical Characteristics for AC

Symbol	Parameter	VCC	TA = + 25° C			TA = − 40° C to + 85° C	Units		Conditions
		(V)	Typ		Guaranteed Limits
VIH	Minimum HIGH Level	3.0	1.5	2.1		2.1		VOUT =		0.1V
	Input Voltage	4.5	2.25	3.15		3.15	V	or VCC −			0.1V
		5.5	2.75	3.85		3.85
VIL	Maximum LOW Level	3.0	1.5	0.9		0.9		VOUT =		0.1V
	Input Voltage	4.5	2.25	1.35		1.35	V	or VCC −			0.1V
		5.5	2.75	1.65		1.65
VOH	Minimum HIGH Level	3.0	2.99	2.9		2.9
	Output Voltage	4.5	4.49	4.4		4.4	V	IOUT =		−	50 µ A
		5.5	5.49	5.4		5.4
								VIN =	VIL or VIH
		3.0		2.56		2.46		IOH =	−	12 mA
		4.5		3.86		3.76	V	IOH =	−	24 mA
		5.5		4.86		4.76		IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	3.0	0.002	0.1		0.1
	Output Voltage	4.5	0.001	0.1		0.1	V	IOUT =		50 µ A
		5.5	0.001	0.1		0.1
								VIN =	VIL or VIH
		3.0		0.36		0.44		IOL =	12 mA
		4.5		0.36		0.44	V	IOL =	24 mA
		5.5		0.36		0.44		IOL =	24 mA (Note 2)
IIN	Maximum Input	5.5		± 0.1		± 1.0	µ A	VI =	VCC, GND
(Note 4)	Leakage Current
IOLD	Minimum Dynamic	5.5				75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 3)	5.5				− 75	mA	VOHD =			3.85V Min
ICC	Maximum Quiescent	5.5		4.0		40.0	µ A	VIN =	VCC or GND
(Note 4)	Supply Current

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

74ACT175 • 74AC175

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