Fairchild Semiconductor 74ACT245SJX, 74ACT245SC, 74ACT245PC, 74ACT245MTCX, 74ACT245MTC Datasheet

November 1988

Revised November 1999

74AC245 • 74ACT245

Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs

General Description

The AC/ACT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-ori- ented applications. Current sinking capability is 24 mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW) enables data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.

Features

■ICC and IOZ reduced by 50%

■Noninverting buffers

■Bidirectional data path

■A and B outputs source/sink 24 mA

■ACT245 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74AC245SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC245SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC245MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC245PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT245SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT245SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT245MSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT245MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT245PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

FACT is a trademark of Fairchild Semiconductor Corporation.

STATE-3 with Transceiver Bidirectional Octal 74ACT245 • 74AC245

© 1999 Fairchild Semiconductor Corporation

DS009944

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74AC245 • 74ACT245

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Descriptions

			Pin			Description
		Names
						Output Enable Input
		OE
						Transmit/Receive Input
	T/R
	A0–A7					Side A 3-STATE Inputs or 3-STATE Outputs
	B0–B7					Side B 3-STATE Inputs or 3-STATE Outputs
Truth Table

		Inputs				Outputs
OE			T/R
	L		L			Bus B Data to Bus A
	L		H			Bus A Data to Bus B
	H		X			HIGH-Z State

H =	HIGH Voltage Level
L =	LOW Voltage Level
X =	Immaterial

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V	− 20 mA
VI =	VCC + 0.5V	+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V	− 20 mA
VO =	VCC + 0.5V	+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		± 50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
Junction Temperature (TJ)
PDIP		140° C

Recommended Operating

Conditions

Supply Voltage (VCC)
AC	2.0V to 6.0V
ACT	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V	125 mV/ns
Minimum Input Edge Rate (∆ V/∆ t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics for AC

		V	TA = + 25° C				TA = − 40° C to + 85° C
Symbol	Parameter	CC						Units		Conditions
		(V)	Typ			Guaranteed Limits
VIH	Minimum HIGH Level	3.0	1.5		2.1		2.1		VOUT =		0.1V
	Input Voltage	4.5	2.25	3.15			3.15	V	or VCC −			0.1V
		5.5	2.75	3.85			3.85
VIL	Maximum LOW Level	3.0	1.5		0.9		0.9		VOUT =		0.1V
	Input Voltage	4.5	2.25	1.35			1.35	V	or VCC −			0.1V
		5.5	2.75	1.65			1.65
VOH	Minimum HIGH Level	3.0	2.99		2.9		2.9
	Output Voltage	4.5	4.49		4.4		4.4	V	IOUT =		−	50 µ A
		5.5	5.49		5.4		5.4
									VIN =	VIL or VIH
		3.0		2.56			2.46		IOH =	−	12 mA
		4.5		3.86			3.76	V	IOH =	−	24 mA
		5.5		4.86			4.76		IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	3.0	0.002		0.1		0.1
	Output Voltage	4.5	0.001		0.1		0.1	V	IOUT =		50 µ A
		5.5	0.001		0.1		0.1
									VIN =	VIL or VIH
		3.0		0.36			0.44		IOL =	12 mA
		4.5		0.36			0.44	V	IOL =	24 mA
		5.5		0.36			0.44		IOL =	24 mA (Note 2)
IIN (Note 4)	Maximum Input Leakage Current	5.5		±	0.1		± 1.0	µ A	VI =	VCC, GND
IOLD	Dynamic Output	5.5					75	mA	VOLD =		1.65V Max
IOHD	Current Minimum (Note 3)	5.5					− 75	mA	VOHD =			3.85V Min
ICC (Note 4)	Maximum Quiescent Supply Current	5.5			4.0		40.0	µ A	VIN =	VCC or GND
IOZT	Maximum I/O								VI (OE) = VIL, VIH
	Leakage Current	5.5		±	0.3		± 3.0	µ A	VI =	VCC, GND
									VO =	VCC, GND

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

74ACT245 • 74AC245

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