August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP), Clear (CLR), Clock Enable (EN) and Output Enable (OE) are common to each byte and can be shorted together for full 18-bit operation.
Features
■Broadside pinout allows for easy board layout
■Separate control logic for each byte
■Extra data width for wider address/data paths or buses carrying parity
■Outputs source/sink 24 mA
■TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACT18823SSC |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ACT18823MTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagram |
Pin Descriptions
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Pin Names |
Description |
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n |
Output Enable Input (Active LOW) |
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OE |
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Clear (Active LOW) |
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CLR |
n |
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Clock Enable (Active LOW) |
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EN |
n |
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CPn |
Clock Pulse Input |
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I0–I17 |
Inputs |
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O0–O17 |
Outputs |
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FACTä is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Flop-Flip Type-D Bit-18 74ACT18823
© 1999 Fairchild Semiconductor Corporation |
DS500294 |
www.fairchildsemi.com |
74ACT18823
Functional Description
The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock (CPn) and buffered Output Enable (OEn) are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With
OEn LOW, the contents of the flip-flops are available at the
outputs. When OEn is HIGH, the outputs go to the imped-
ance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLRn) and Clock Enable
(ENn) pins. These devices are ideal for parity bus interfacing in high performance systems.
When CLRn is LOW and OEn is LOW, the outputs are
LOW. When CLRn is HIGH, data can be entered into the
flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Logic Diagrams
Function Table
(Note 1)
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Inputs |
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Internal |
Output |
Function |
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OE |
CLR |
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EN |
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CP |
In |
Q |
On |
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H |
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X |
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L |
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L |
L |
Z |
High Z |
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H |
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X |
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L |
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H |
H |
Z |
High Z |
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H |
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L |
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X |
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X |
X |
L |
Z |
Clear |
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L |
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L |
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X |
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X |
X |
L |
L |
Clear |
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H |
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H |
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H |
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X |
X |
NC |
Z |
Hold |
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L |
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H |
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H |
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X |
X |
NC |
NC |
Hold |
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H |
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H |
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L |
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L |
L |
Z |
Load |
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H |
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H |
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L |
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H |
H |
Z |
Load |
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L |
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H |
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L |
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L |
L |
L |
Load |
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L |
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H |
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L |
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H |
H |
H |
Load |
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H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC= No Change
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
Byte 1 (0:8)
Byte 2 (9:17)
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