THS5671A 14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
DMember of the Pin-Compatible CommsDAC Product Family
D125 MSPS Update Rate
D14-Bit Resolution
DSpurious Free Dynamic Range (SFDR) to Nyquist at 40 MHz Output: 63 dBc
D1 ns Setup/Hold Time
DDifferential Scalable Current Outputs: 2 mA to 20 mA
DOn-Chip 1.2 V Reference
D3 V and 5 V CMOS-Compatible Digital Interface
DStraight Binary or Twos Complement Input
DPower Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V
SOIC (DW) OR TSSOP (PW) PACKAGE
(TOP VIEW)
D13 |
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1 |
28 |
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CLK |
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D12 |
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2 |
27 |
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DVDD |
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D11 |
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3 |
26 |
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DGND |
D10 |
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4 |
25 |
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MODE |
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D9 |
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5 |
24 |
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AVDD |
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D8 |
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6 |
23 |
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COMP2 |
D7 |
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22 |
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IOUT1 |
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D6 |
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21 |
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IOUT2 |
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D5 |
9 |
20 |
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AGND |
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D4 |
10 |
19 |
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COMP1 |
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D3 |
11 |
18 |
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BIASJ |
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D2 |
12 |
17 |
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EXTIO |
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D1 |
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16 |
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EXTLO |
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D0 |
14 |
15 |
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SLEEP |
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DPackage: 28-Pin SOIC and TSSOP
description
The THS5671A is a 14-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data transmission in wired and wireless communication systems. The 14-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package, and pinout. The THS5671A offers superior ac and dc performance while supporting update rates up to 125 MSPS.
The THS5671A operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW ensures that the device is well-suited for portable and low-power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power consumption for system needs.
The THS5671A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature-compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5671A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors.
The THS5671A provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC. The output voltage compliance range is 1.25 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CommsDAC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
THS5671A
14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
description (continued)
The THS5671A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of ±40°C to 85°C.
AVAILABLE OPTIONS
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PACKAGE |
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TA |
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28-TSSOP |
28-SOIC |
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(PW) |
(DW) |
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± 40°C to 85°C |
THS5671AIPW |
THS5671AIDW |
functional block diagram |
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AVDD |
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C1 |
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SLEEP |
COMP1 |
0.1 µF |
COMP2 |
0.1 µF |
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EXTLO |
1.2 V |
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REF |
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1 nF |
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IOUT1 |
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EXTIO |
± |
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Output |
50 Ω |
RLOAD |
CEXT |
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Current |
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Source |
Current |
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BIASJ |
+ |
Control |
Array |
Switches |
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0.1 µF |
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AMP |
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I BIAS |
IOUT2 |
2 kΩ RBIAS |
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DVDD |
50 Ω RLOAD |
Logic
D[13:0]
Control
MODE |
CLK |
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DGND |
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AGND |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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THS5671A |
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14-BIT, 125 MSPS, CommsDAC |
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DIGITAL-TO-ANALOG CONVERTER |
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SLAS201 ± DECEMBER 1999 |
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Terminal Functions |
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TERMINAL |
I/O |
DESCRIPTION |
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NAME |
NO. |
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AGND |
20 |
I |
Analog ground return for the internal analog circuitry |
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AVDD |
24 |
I |
Positive analog supply voltage (4.5 V to 5.5 V) |
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BIASJ |
18 |
O |
Full-scale output current bias |
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CLK |
28 |
I |
External clock input. Input data latched on rising edge of the clock. |
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COMP1 |
19 |
I |
Compensation and decoupling node, requires a 0.1 F capacitor to AVDD. |
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COMP2 |
23 |
I |
Internal bias node, requires a 0.1 F decoupling capacitor to AGND. |
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D[13:0] |
[1:14] |
I |
Data bits 0 through 13. |
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D13 is most significant data bit (MSB), D0 is least significant data bit (LSB). |
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DGND |
26 |
I |
Digital ground return for the internal digital logic circuitry |
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DVDD |
27 |
I |
Positive digital supply voltage (3 V to 5.5 V) |
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EXTIO |
17 |
I/O |
Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal |
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reference output when EXTLO = AGND, requires a 0.1 F decoupling capacitor to AGND when used as reference |
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output. |
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EXTLO |
16 |
O |
Internal reference ground. Connect to AVDD to disable the internal reference source. |
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IOUT1 |
22 |
O |
DAC current output. Full scale when all input bits are set 1 |
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IOUT2 |
21 |
O |
Complementary DAC current output. Full scale when all input bits are 0 |
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MODE |
25 |
I |
Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See |
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timing diagram. |
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SLEEP |
15 |
I |
Asynchronous hardware power down input. Active high. Internal pulldown. Requires 5 s to power down but 3 ms |
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to power up. |
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)²
Supply voltage range, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.3 V to 6.5 V |
DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.3 V to 6.5 V |
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.3 V to 0.5 V |
Supply voltage range, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±6.5 V to 6.5 V |
CLK, SLEEP, MODE (see Note 2) . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to DVDD + 0.3 V |
Digital input D13±D0 (see Note 2) . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to DVDD + 0.3 V |
IOUT1, IOUT2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. ±1 V to AVDD + 0.3 V |
COMP1, COMP2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to AVDD + 0.3 V |
EXTIO, BIASJ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to AVDD + 0.3 V |
EXTLO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.3 V to 0.3 V |
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . 20 mA |
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . ±30 mA |
Operating free-air temperature range, TA: THS5671AI . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±40°C to 85°C |
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±65°C to 150°C |
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . 260°C |
² Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Measured with respect to AGND. 2. Measured with respect to DGND.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
THS5671A
14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)
dc specifications
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PARAMETER |
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TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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Resolution |
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14 |
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Bits |
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DC accuracy² |
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INL |
Integral nonlinearity |
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TA = ±40°C to 85°C |
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±7 |
±2.5 |
7 |
LSB |
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DNL |
Differential nonlinearity |
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±3.5 |
±2 |
3.5 |
LSB |
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Monotonicity |
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At 11-bit level |
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Monotonic |
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Analog output |
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Offset error |
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%FSR |
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Gain error |
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Without internal reference |
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%FSR |
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With internal reference |
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1.3 |
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Full scale output current³ |
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20 |
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Output compliance range |
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AVDD = 5 V, |
IOUTFS = 20 mA |
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1.25 |
V |
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300 |
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Output capacitance |
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pF |
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Reference output |
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Reference voltage |
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1.18 |
1.22 |
1.32 |
V |
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Reference output current§ |
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100 |
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Reference input |
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VEXTIO |
Input voltage range |
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0.1 |
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1.25 |
V |
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Input resistance |
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1 |
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Small signal bandwidth¶ |
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pF |
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0 |
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Power supply |
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AVDD |
Analog supply voltage |
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4.5 |
5 |
5.5 |
V |
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DVDD |
Digital supply voltage |
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3 |
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IAVDD |
Analog supply current |
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Sleep mode supply current |
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Sleep mode |
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3 |
5 |
mA |
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I |
Digital supply current# |
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5 |
6 |
mA |
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DVDD |
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Power dissipation|| |
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AVDD = 5 V, |
DVDD = 5 V, IOUTFS = 20 mA |
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175 |
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mW |
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AVDD |
Power supply rejection ratio |
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DVDD |
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Operating range |
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±40 |
|
85 |
°C |
||||
² Measured at IOUT1 in virtual ground configuration. |
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|||||||||
³ Nominal full-scale current IOUTFS equals 32X the IBIAS current. |
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||||||||||
§ Use an external buffer amplifier with high impedance input to drive any external load. |
|
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|
||||||||||||
¶ Reference bandwidth is a function of external cap at COMP1 pin and signal level. |
|
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|
||||||||||||
# Measured at f |
CLK |
= 50 MSPS and f |
= 1 MHz. |
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||||
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OUT |
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||
|| Measured for 50 |
Ω R |
LOAD |
at IOUT1 and IOUT2, f |
CLK |
= 50 MSPS and f |
= 20 MHz. |
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||||||
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OUT |
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|
Specifications subject to change
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS5671A 14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load
(unless otherwise noted)
ac specifications
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|
|
|
|
|
|
|
|
|
Analog output |
|
|
|
|
|
||
|
|
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|
|
|
|
|
fCLK |
Maximum output update rate |
DVDD = 4.5 V to 5.5 V |
100 |
125 |
|
MSPS |
|
DVDD = 3 V to 3.6 V |
70 |
100 |
|
||||
|
|
|
|
|
|||
t |
Output settling time to 0.1%² |
|
|
35 |
|
ns |
|
s(DAC) |
|
|
|
|
|
|
|
tpd |
Output propagation delay |
|
|
1 |
|
ns |
|
GE |
Glitch energy³ |
|
Worst case LSB transition (code 8191 ± code 8192) |
|
5 |
|
pV-s |
t |
Output rise time 10% to 90%² |
|
|
1 |
|
ns |
|
r(IOUT) |
|
|
|
|
|
|
|
t |
Output fall time 90% to 10%² |
|
|
1 |
|
ns |
|
f(IOUT) |
|
|
|
|
|
|
|
|
Output noise |
IOUTFS = 20 mA |
|
15 |
|
pA/√ HZ |
|
|
IOUTFS = 2 mA |
|
10 |
|
|||
|
|
|
|
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|
||
AC linearity§ |
|
|
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|
|
||
|
|
|
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C |
|
±74 |
|
|
THD |
Total harmonic distortion |
fCLK = 50 MSPS, fOUT = 1 MHz, TA = ±40°C to 85°C |
|
±73 |
±66 |
dBc |
|
fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25°C |
|
±71 |
|
||||
|
|
|
|
|
|
||
|
|
|
fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25°C |
|
±71 |
|
|
|
|
|
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C |
|
82 |
|
|
|
|
|
fCLK = 50 MSPS, fOUT= 1 MHz, TA = ±40°C to 85°C |
68 |
|
|
|
|
|
|
fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C |
|
82 |
|
dBc |
|
Spurious free dynamic range to |
fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25°C |
|
75 |
|
||
|
|
|
|
||||
|
fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25°C |
|
74 |
|
|
||
|
Nyquist |
|
|
|
|||
SFDR |
fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25°C |
|
57 |
|
|
||
|
|
|
|
|
|||
|
|
fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25°C |
|
70 |
|
dBc |
|
|
|
|
|
|
|||
|
|
|
fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25°C |
|
66 |
|
dBc |
|
|
|
fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25°C |
|
63 |
|
dBc |
|
Spurious free dynamic range |
fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25°C,1 MHz span |
|
90 |
|
|
|
|
fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span |
|
89 |
|
dBc |
||
|
within a window |
|
|
||||
|
fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span |
|
89 |
|
|
||
|
|
|
|
|
|
||
² Measured single ended into 50 Ω load at IOUT1. |
|
|
|
|
|||
³ Single-ended output IOUT1, 50 Ω doubly terminated load. |
|
|
|
|
§Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range from 45%/55% to 55%/45%.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
THS5671A
14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)
digital specifications
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|
|
|
|
|
|
|
Interface |
|
|
|
|
|
|
|
|
|
|
|
|
|
VIH |
High-level input voltage |
DVDD = 5 V |
3.5 |
5 |
|
V |
DVDD = 3.3 V |
2.1 |
3.3 |
|
|||
|
|
|
|
|||
VIL |
Low-level input voltage |
DVDD = 5 V |
|
0 |
1.3 |
V |
DVDD = 3.3 V |
|
0 |
0.9 |
|||
|
|
|
|
|||
IIH |
High-level input current |
DVDD = 3 V to 5.5 V |
±10 |
|
10 |
A |
IIL |
Low-level input current |
DVDD = 3 V to 5.5 V |
±10 |
|
10 |
A |
|
Input capacitance |
|
1 |
|
5 |
pF |
|
|
|
|
|
|
|
Timing |
|
|
|
|
|
|
|
|
|
|
|
|
|
tsu(D) |
Input setup time |
|
1 |
|
|
ns |
th(D) |
Input hold time |
|
1 |
|
|
ns |
tw(LPH) |
Input latch pulse high time |
|
4 |
|
|
ns |
td(D) |
Digital delay time |
|
|
|
1 |
clk |
Specifications subject to change
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS5671A 14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
TYPICAL CHARACTERISTICS²
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 0 dBFS
|
90 |
|
|
|
|
|
dBc |
|
|
|
DVDD = 5 V |
|
|
84 |
|
|
|
|
|
|
± |
|
|
|
|
|
|
|
|
|
|
|
|
|
Range |
|
fCLK = 5 MSPS |
|
|
|
|
78 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Dynamic |
72 |
fCLK = 50 MSPS |
|
|
|
|
|
|
|
|
|
||
|
|
fCLK |
= 70 MSPS |
|
|
|
Free |
66 |
|
|
|
||
|
|
fCLK = 100 MSPS |
|
|||
|
|
|
|
|||
± Spurious |
|
|
|
|
||
60 |
|
|
|
|
|
|
54 |
fCLK = 25 MSPS |
|
|
|
||
SFDR |
|
|
|
|
|
|
48 |
|
fCLK |
= 125 MSPS |
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
0 |
10 |
20 |
30 |
40 |
50 |
|
|
Fout ± Output Frequency ± MHz |
|
Figure 1
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 25 MSPS
|
90 |
|
|
|
|
|
|
± dBc |
|
|
|
|
|
DVDD = 5 V |
|
|
|
|
|
|
|
|
|
Range |
84 |
|
|
|
|
|
|
|
|
0 dBFS |
|
|
|
|
|
Free Dynamic |
78 |
|
|
±6 dBFS |
|
|
|
72 |
|
|
|
|
|
|
|
Spurious |
|
|
|
|
|
|
|
|
±12 dBFS |
|
|
|
|
||
66 |
|
|
|
|
|
|
|
SFDR ± |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
60 |
|
|
|
|
|
|
|
0 |
2 |
4 |
6 |
8 |
10 |
12 |
|
|
|
Fout ± Output Frequency ± MHz |
|
Figure 3
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 5 MSPS
|
90 |
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
± dBc |
|
|
|
|
|
|
|
|
DVDD = 5 V |
|
|
|
|
|||||
84 |
|
|
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Range |
|
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||
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|
0 dBFS |
|
|
|
||||
|
|
|
|
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|
|
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|
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|
||||
Dynamic |
78 |
|
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||
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|
|
|
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|
|
Free |
|
|
|
|
|
|
|
|
|
|
|
±6 dBFS |
|
|
|
|
||
72 |
|
|
|
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|
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|
|
|
|
|
|
|
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||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Spurious |
66 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
±12 dBFS |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
SFDR ± |
60 |
|
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||
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||
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|
|
0 |
0.5 |
1.0 |
1.5 |
2.0 |
|
|
2.5 |
Fout ± Output Frequency ± MHz
Figure 2
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 50 MSPS
|
78 |
|
|
|
|
|
± dBc |
|
|
±6 dBFS |
DVDD = 5 V |
|
|
|
|
|
|
|
|
|
Range |
72 |
|
|
±12 dBFS |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
Free Dynamic |
66 |
|
0 dBFS |
|
|
|
|
|
|
|
|
||
60 |
|
|
|
|
|
|
Spurious |
|
|
|
|
|
|
54 |
|
|
|
|
|
|
SFDR ± |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
48 |
|
|
|
|
|
|
0 |
5 |
10 |
15 |
20 |
25 |
|
|
Fout ± Output Frequency ± MHz |
|
Figure 4
²AV DD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
7 |
THS5671A
14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
TYPICAL CHARACTERISTICS²
|
|
|
SPURIOUS FREE DYNAMIC RANGE |
|
|
||||||||||
|
|
|
|
|
|
|
vs |
|
|
|
|
|
|
|
|
|
|
|
OUTPUT FREQUENCY AT 70 MSPS |
|
|
||||||||||
dBc |
78 |
|
|
|
|
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|
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||
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|
|
DVDD = 5 V |
|
|
||||
± |
|
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Range |
72 |
|
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|
Dynamic |
|
|
|
|
|
|
±12 dBFS |
|
|
|
|
|
|||
66 |
|
|
|
|
|
|
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|
|
|
|
|
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|
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|
|
±6 dBFS |
|
|
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|
||||
Free |
|
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|
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|
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|
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|
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60 |
|
|
0 dBFS |
|
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|
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||
|
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|
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|
|||
Spurious |
|
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|
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|
54 |
|
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SFDR ± |
|
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||
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48 |
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|
0 |
10 |
|
20 |
30 |
|
40 |
Fout ± Output Frequency ± MHz
Figure 5
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 125 MSPS
|
78 |
|
|
|
|
|
± dBc |
|
|
|
|
DVDD = 5 V |
|
|
|
|
|
|
|
|
Range |
72 |
|
|
|
|
|
|
|
|
±6 dBFS |
|
||
Free Dynamic |
|
|
|
|
||
66 |
|
|
|
±12 dBFS |
|
|
|
|
|
|
|
||
60 |
|
|
|
|
|
|
Spurious |
|
|
|
|
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|
|
0 dBFS |
|
|
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|
|
54 |
|
|
|
|
|
|
SFDR ± |
|
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|
|
48 |
|
|
|
|
|
|
0 |
10 |
20 |
30 |
40 |
50 |
|
|
Fout ± Output Frequency ± MHz |
|
Figure 7
|
|
|
SPURIOUS FREE DYNAMIC RANGE |
|
|
||||||||||
|
|
|
|
|
|
|
|
|
vs |
|
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|
||
|
|
|
OUTPUT FREQUENCY AT 100 MSPS |
|
|
||||||||||
|
78 |
|
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dBc |
|
|
|
|
|
±12 dBFS |
|
|
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|
||
|
|
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|
|
|
|
|
DVDD = 5 V |
|
|
|||||
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|||
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|||
± |
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Range |
72 |
|
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|
±6 dBFS |
|
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DynamicFree |
66 |
|
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0 dBFS |
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Spurious |
60 |
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54 |
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SFDR ± |
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48 |
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0 |
10 |
20 |
30 |
40 |
50 |
Fout ± Output Frequency ± MHz
Figure 6
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 0 dBFS
|
90 |
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dBc |
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fCLK = 5 MSPS |
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DVDD = 3.3 V |
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84 |
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± |
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Range |
78 |
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Dynamic |
72 |
fCLK = 50 MSPS |
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66 |
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fCLK = 100 MSPS |
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Free |
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60 |
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Spurious |
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54 |
fCLK = 25 MSPS |
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± |
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SFDR |
48 |
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42 |
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0 |
10 |
20 |
30 |
40 |
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Fout ± Output Frequency ± MHz |
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Figure 8
²AV DD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)
8 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS5671A 14-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201 ± DECEMBER 1999
TYPICAL CHARACTERISTICS²
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 5 MSPS
|
90 |
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± dBc |
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DVDD = 3.3 V |
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0 dBFS |
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Range |
84 |
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Dynamic |
78 |
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±6 dBFS |
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Free |
72 |
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±12 dBFS |
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Spurious |
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66 |
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SFDR ± |
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60 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
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Fout ± Output Frequency ± MHz |
|
Figure 9
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 50 MSPS
|
78 |
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± dBc |
72 |
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0 |
dBFS |
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DVDD |
= 3.3 V |
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Range |
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±6 dBFS |
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DynamicFree |
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66 |
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±12 dBFS |
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Spurious |
60 |
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54 |
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SFDR ± |
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48 |
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0 |
5 |
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10 |
15 |
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20 |
25 |
Fout ± Output Frequency ± MHz
Figure 11
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 25 MSPS
|
90 |
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± dBc |
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DVDD = 3.3 V |
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Range |
84 |
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±6 dBFS |
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Free Dynamic |
|
|
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|
78 |
|
|
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|
72 |
|
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Spurious |
|
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±12 dBFS |
|
|
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|
66 |
|
0 dBFS |
|
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SFDR ± |
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60 |
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0 |
2 |
4 |
6 |
8 |
10 |
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Fout ± Output Frequency ± MHz |
|
Figure 10
SPURIOUS FREE DYNAMIC RANGE vs
OUTPUT FREQUENCY AT 70 MSPS
|
78 |
|
|
|
|
± dBc |
|
|
|
DVDD = 3.3 V |
|
|
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Range |
72 |
0 dBFS |
|
|
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||
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|
|
Free Dynamic |
66 |
|
|
±6 dBFS |
|
|
|
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|
||
60 |
±12 dBFS |
|
|
|
|
Spurious |
|
|
|
||
54 |
|
|
|
|
|
SFDR ± |
|
|
|
|
|
|
|
|
|
|
|
|
48 |
|
|
|
|
|
0 |
10 |
20 |
30 |
40 |
Fout ± Output Frequency ± MHz
Figure 12
²AV DD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
9 |