Texas Instruments THS8134EVM, THS8134CPHP, THS8134BCPHP, THS8134AEVM, THS8134ACPHP Datasheet

0 (0)

features

DTriple 8-Bit D/A Converters

DMinimum 80 MSPS Operation

DDirect Drive of Doubly-Terminated 75-Ω

Load Into Standard Video Levels

D3×8 Bit 4:4:4, 2×8 Bit 4:2:2 or 1×8 Bit 4:2:2

(ITU-BT.656) Multiplexed YPbPr/GBR Input Modes

DBi-Level (EIA) or Tri-Level (SMPTE) Sync Generation With 7:3 Video/Sync Ratio

DIntegrated Insertion of Sync-On-Green/ Luminance or Sync-On-All Channels

DConfigurable Blanking Level

DInternal Voltage Reference

applications

DHigh-Definition Television (HDTV) Set-Top Boxes/Receivers

DHigh-Resolution Image Processing

DDesktop Publishing

DDirect Digital Synthesis/I-Q Modulation

THS8134, THS8134A, THS8134B TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

TQFP-48 PowerPAD PACKAGE

(TOP VIEW)

ABPb

ARPr

AGY

COMP

FSADJ

REF

48 47 46 45 44 43 42 41 40 39 38 37

BPb7

BPb6

GY0

BPb5

GY1

BPb4

GY2

BPb3

GY3

BPb2

GY4

BPb1

GY5

BPb0

GY6

GY7

DVSS

CLK

SYNC_T

DVDD

14 15 16 17 18 19

20 21 22 23 24

RPr0

RPr1

RPr2

RPr3

RPr4

RPr5

RPr6

RPr7

BLANK

SYNC

See ALSO: THS8133 (10 bit, pin-compatible)

description

The THS8134 is a general-purpose triple high-speed D/A converter (DAC) optimized for use in video/graphics applications. The device operates from a 5-V analog supply and a 3-V to 5-V range digital supply. The THS8134 has a sampling rate up to 80 MSPS. The device consists of three 8-bit D/A converters and additional circuitry for bi-level/tri-level sync and blanking level generation in video applications.

THS8134 is also well-suited in applications where multiple well-matched and synchronously operating DACs are needed; for example, I-Q modulation and direct-digital synthesis in communications equipment.

The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device provides a flexible configuration of maximum output current drive. Its output drivers are specifically designed to produce standard video output levels when directly connected to a single-ended doubly-terminated 75 Ω coaxial cable. Full-scale video/sync is generated in a 7:3 ratio, compliant with SMPTE standards for GBR and YPbPr signals.

Furthermore, the THS8134 can generate both a traditional bi-level sync or a tri-level sync signal, as per the SMPTE standards, via a digital control interface. The sync signal is inserted on one of the analog output channels (sync-on-green/luminance) or on all output channels. Also, a blanking control signal sets the outputs to defined levels during the nonactive video window.

The position of this defined (blanking) level and the temperature range, over which the maximum imbalance

between the inserted analog syncs (KIMBAL(SYNC)), are the only differences between the unrev, revA, and revB device versions. Refer to the Available Options table.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

description (continued)

Finally the input format can be either 3×8 bit 4:4:4, 2×8 bit 4:2:2, or 1×8 bit 4:2:2. This enables a direct interface to a wide range of video DSP/ASICs including parts generating ITU-BT.656 formatted output data.

AVAILABLE OPTIONS
TA		PACKAGE

		TQFP-48 PowerPAD


		THS8134CPHP²
0°C to 70°C		THS8134ACPHP³
		THS8134BCPHP³
² In the THS8134CPHP, the K		maximum specification is
		IMBAL
assured over full temperature range and the KIMBAL(SYNC)
maximum specification is assured at 25°C. The position of
the blanking level is as shown in Table 1.
³ In the THS8134ACPHP and the THS8134BCPHP, both the
KIMBALmaximum specification and the KIMBAL(SYNC)
maximum specification are assured over the full temperature
range. The position of the blanking level is as shown in
Table 1.

			Terminal Functions

TERMINAL		I/O	DESCRIPTION
NAME	PIN	I/O	DESCRIPTION
NAME	PIN

ABPb	45	O	Analog red, green and blue respectively Pr, Y and Pb current outputs, capable of directly driving a doubly
			terminated 75-Ω coaxial cable.
AGY	41	O	terminated 75-Ω coaxial cable.
AGY	41	O

ARPr	43	O

AVDD	40,44	I	Analog power supply (5 V ±10%). All AVDD terminals must be connected.
AVSS	42,46	I	Analog ground
	23	I	Blanking control input, active low. A rising edge on CLK latches			When asserted, the ARPr, AGY and
BLANK	23	I		BLANK.		When asserted, the ARPr, AGY and
			ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
			precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation.

BPb0±BPb7	8±1	I	Blue or Pb pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
			different operating modes.

CLK	26	I	Clock input. A rising edge on CLK latches RPr0-7, GY0-7, BPb0-7,					and SYNC_T. The M2 input is
CLK	26	I			BLANK,		SYNC,	and SYNC_T. The M2 input is
			latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its
			terminal description.

COMP	39	O	Compensation terminal. A 0.1 µF capacitor must be connected between COMP and AVDD.
DVDD	12	I	Digital power supply (3-V to 5-V range)
DVSS	11	I	Digital ground
FSADJ	38	I	Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of
			a resistor RFS connected between this terminal and AVSS. The nominal value of RFS is 430 Ω, corresponding to
			26.67 mA full-scale current. The relationship between RFS and the full-scale current level for each operation
			mode is explained in the functional description.
GY0±GY7	34±27	I	Green or Y pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
			different operating modes.

M1	47	I	Operation mode control 1. M1 is directly interpreted by the device (it is not latched by CLK). M1 configures device
			according to Table 1.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

Operation mode control 2. The second rising edge on CLK after a transition on

SYNC

latches M2. The

interpretation is dependent on the polarity of the last

SYNC

transition:

SYNC L to H: latched as M2_INT

SYNC H to L: latched as INS3_INT

Together with M1, M2_INT configures the device as shown in Table 1. When INS3_INT is high, the sync output is

inserted on all DAC outputs; a low will insert it only on the AGY output. See also Figure 2 and Table 2. The value of

M2 at power-up is undetermined. Therefore at least 1 L → H transition on SYNC is required to set M2.

9, 10,

Not connected

13, 14,

35, 36

RPr0±RPr7

15±22

Red or Pr pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for different

operating modes.

Sync control input, active low. A rising edge on CLK latches

When asserted, only the AGY output

SYNC

SYNC.

(INS3_INT=L, see terminal M2) or ARPr, AGY and ABPb outputs (INS3_INT=H, see terminal M2) are driven to

the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low

for the whole duration of sync, which is in the case of a tri-level sync both the negative and positive portion (see

Figure 7).

SYNC_T

Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher

than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level)

is generated when

SYNC

is low. When generating a tri-level (negative-to-positive) sync, a L → H transition on

this signal positions the start of the positive transition. See Figure 6 for timing control.

The value on SYNC_T is ignored when

SYNC

is not asserted (high).

VREF

I/O

Voltage reference for DACs. An internal voltage reference of nominally 1.35 V is provided, which requires an

external 0.1 µF ceramic capacitor between VREF and AVSS. However, the internal reference can be overdriven

by an externally supplied reference voltage.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

		FSADJ
	DVDD DVSS	COMP	VREF
		Bandgap
		Reference
RPr[7:0]		R/Pr	DAC	ARPr
RPr[7:0]		Register	DAC	ARPr
		Register
GY[7:0]	Input	G/Y	DAC	AGY
	Formatter	Register	DAC	AGY
	Formatter	Register
BPb[7:0]		B/Pb	DAC	ABPb
BPb[7:0]		Register	DAC	ABPb
		Register

CLK	Configuration	SYNC/BLANK
M1	Configuration	SYNC/BLANK
M1	Control	Control
M2	Control	Control
M2
	AVDD AVSS	SYNC	BLANK
		SYNC_T

Figure 1. THS8134 Block Diagram

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

functional description

device configuration

Input data to the device can be supplied from a 3x8b GBR/YPbPr input port. If the device is configured to take data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at the full clock speed of CLK.

In the case of 4:2:2 sampled data (for YPbPr) the device can be fed over either a 2x8 bit or 1x8 bit multiplexed input port. An internal demultiplexer will route input samples to the appropriate DAC: Y at the rate of CLK, Pb and Pr each at the rate of one-half CLK.

According to ITU-BT.656, the sample sequence is Pb-Y-Pr over a 1x8 bit interface (Y-port). The sample sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). In this case the frequency of CLK is two times the Y conversion speed and four times the conversion speed of both Pr and Pb.

With a 2x8 bit input interface, both the Y-port and the Pr-port are sampled on every CLK rising edge. The Pr-port carries the sample sequence Pb-Pr. The sample sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). In this case the frequency of CLK is equal to the conversion speed of Y and 2x the conversion speed of both Pr and Pb.

The device's operation mode is set by the M1 and M2 mode selection terminals, according to Table 1. The operation mode also determines the blanking level, as explained below in the sync/blanking generation sections.

			Table 1. THS8134 Configuration

M1	M2_INT	CONFIGURATION	DESCRIPTION

L	L	GBR	GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels. For the
		3x8b±4:4:4	definition of the analog output levels during blanking, see note 1.

L	H	YPbPr	YPbPr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Pb and Pr input channels. For
		3x8b±4:4:4	the definition of the analog output levels during blanking, see note 1.

H	L	YPbPr	YPbPr mode 4:2:2 2x8 bit. Data clocked in on each rising edge of CLK from Y & Pr input channels. A
		2x8b±4:2:2	sample sequence of Pb±Pr±... should be applied to the Pr port. At the first rising edge of CLK after
			BLANK is taken high, Pb should be present on this port. For the definition of the analog output levels
			during blanking, see note 1.

H	H	YPbPr	YPbPr mode 4:2:2 1x8 bit (ITU-BT.656 compliant). Data clocked in on each rising edge of CLK from Y
		1x8b±4:2:2	input channel. For the definition of the analog output levels during blanking, see note 1.

NOTE 1: In all device versions, the blanking level on the AGY channel output corresponds to input code 0 of the DAC.

•In the THS8134CPHP and the THS8134ACPHP versions, the blanking level on the ABPb and ARPr channel outputs corresponds to the 128 input code of the DAC, when sync is inserted on all three channels (INS3_INT=H), and to the 0 input code of the DAC, when sync is only inserted on the Y channel (INS3_INT=L).

•In the THS8134BCPHP version, the blanking level on the ABPb and ARPr channel outputs corresponds to the 128 input code of the DAC irrespective if sync is inserted on all three channels (INS3_INT=H), or if sync is inserted only on the Y channel (INS3_INT=L).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

			Table 2. INS3_INT/M2_INT Selection on M2

LAST			M2
EVENT ON	SYNC_T	M1	M2			DESCRIPTION
EVENT ON	SYNC_T	M1	(see Note 2)			DESCRIPTION
SYNC			(see Note 2)
SYNC

H→ L
H→ L	L or H	X	INS3_INT	Sync insertion active:	SYNC	low enables sync generation on 1 (INS3_INT=L) or all 3
				(INS3_INT=H) DAC outputs. SYNC_T determines the sync polarity.

L→ H	X	X	M2_INT	Device mode programming active: The DAC outputs reflect the DAC inputs
				(BLANK=H) or are forced to the blanking level (BLANK=L). M2 is interpreted according
				to Table 1.

X = Don't care

NOTE 2: M1 and M2 start configuring the device as soon as they are interpreted, which is continuously for M1 (static pin) or on the second rising edge on CLK after a transition on SYNC for M2. M2 is interpreted as either INS3_INT or M2_INT, as shown in Table 2.

programming example

Configuration of the device will normally be static in a given application. If M2_INT and INS3_INT need to be both low or high, the M2 pin is simply tied low or high. If M2_INT and INS3_INT need to have different levels, these can be easily derived from the signal on the SYNC pin, as shown in Table 3 and Figure 2.

Table 3. Generating M2 From SYNC

In order to have:		Apply to M2:

M2_INT	INS3_INT
M2_INT	INS3_INT

L	H	...		delayed by 2 CLK periods
L	H	...	SYNC	delayed by 2 CLK periods


H	L	...inverted			SYNC	delayed by 2 CLK periods

The input formats and latencies are shown in Figures 3±5 for each operation mode.


	CLK

	SYNC
	M2
		[=SYNC_delayed]
	INS3_INT
if (M2 = SYNC_delayed) M2_INT = L and INS3_INT = H)	M2_INT
	M2_INT
	M2
	[=NOT		SYNC_delayed]
	INS3_INT
if (M2 = NOT SYNC_delayed) M2_INT = H and INS3_INT = L)	M2_INT

Figure 2. Generating INS3_INT and M2_INT from M2

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Texas Instruments THS8134EVM, THS8134CPHP, THS8134BCPHP, THS8134AEVM, THS8134ACPHP Datasheet

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

programming example (continued)

CLK	T0	T1	T2		T3	T4	T5	T6	T7	T8
RPr[7±0]		RPr(0)	RPr(1)	RPr(2)	RPr(3)	RPr(4)	RPr(5)	RPr(6)	RPr(7)	RPr(8)
GY[7±0]		GY(0)	GY(1)	GY(2)	GY(3)	GY(4)	GY(5)	GY(6)	GY(7)	GY(8)
BPb[7±0]		BPb(0)	BPb(1)	BPb(2)	BPb(3)	BPb(4)	BPb(5)	BPb(6)	BPb(7)	BPb(8)

ARPr, AGY,

RPr(0), GY(0), BPb(0)

data path latency = 7 CLK cycles ABPb output

registered

corresponding to RPr(0), GY(0), BPb(0)

Figure 3. Input Format and Latency YPbPr 4:4:4 and GBR 4:4:4 Modes

T0	T1	T2	T3	T4	T5	T6	T7	T8	T9

BLANK

RPr[7±0]

GY[7±0]

BPb[7±0]

First registered sample on RPr[7±0] after L->H on BLANK is interpreted as Pb[7±0]

Pb(0)	Pr(0)	Pb(2)	Pr(2)	Pb(4)	Pr(4)	Pb(6)	Pr(6)	Pb(8)	Pr(8)
Y(0)	Y(1)	Y(2)	Y(3)	Y(4)	Y(5)	Y(6)	Y(7)	Y(8)	Y(9)

			ARPr, AGY,
			ABPb output
		data path latency = 8 CLK cycles
		data path latency = 8 CLK cycles
Pb(0), Y(0)	Pr(0), Y(1)		corresponding to Pr(0),
Pb(0), Y(0)	Pr(0), Y(1)		Y(0), Pb(0)
registered	registered		Y(0), Pb(0)
registered	registered

Figure 4. Input Format and Latency YPbPr 4:2:2 2×8 bit Mode

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D ± MAY 1999 ± REVISED MARCH 2000

programming example (continued)

T10

BLANK

First registered sample on GYr[7±0] after L->H

on BLANK is interpreted as Pb[7±0]

RPr[7±0]

GY[7±0]

Pb(0)

Y(0)

Pr(0)

Y(2)

Pb(4)

Y(4)

Pr(4)

Y(6)

Pb(8)

Y(8)

Pr(8)

BPb[7±0]

ARPr, AGY,

data path latency = 9 CLK cycles

ABPb output

Pb(0)

corresponding

registered

Y(0)

to Pr(0),

registered Pr(0)

Y(0), Pb(0)

registered

Figure 5. Input Format and Latency YPbPr 4:2:2 1×8 bit Mode

sync generation

Additional control inputs SYNC and SYNC_T enable the superposition of an additional current onto the AGY channel or on all three channels, depending on the setting of INS3_INT. By combining the SYNC and SYNC_T control inputs, either bi-level negative going pulses or tri-level pulses can be generated. Depending on the timing controls for these signals, both horizontal and vertical sync signals can be generated. Assertion of SYNC (active low) will identify the sync period, while assertion of SYNC_T (active high) within this period will identify the positive excursion of a tri-level sync.

Refer to the application information section for practical examples on the use of these control inputs for sync generation.

blanking generation

An additional control input BLANK is provided that will fix the output amplitude on all channels to the blanking level, irrespective of the value on the data input ports. However, sync generation has precedence over blanking; that is, if SYNC is low, the level of BLANK is don't care. The absolute amplitude of the blanking level with respect to active video is determined by the GBR or YPbPr operation mode of the device. Refer to the application information section for practical examples on the use of this control input for blank generation.

Figure 6 shows how to control SYNC, SYNC_T, and BLANK signals to generate tri-level sync levels and blanking at the DAC output. A bi-level (negative) sync is generated similarly by avoiding the positive transition on SYNC_T during SYNC low.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

+ 16 hidden pages