Texas Instruments THS6062IDR, THS6062IDGNR, THS6062ID, THS6062IDGN, THS6062EVM Datasheet
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THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
ADSL Differential Receiver
D
Low 1.6 nV/√Hz Voltage Noise
D
High Speed
– 100 MHz Bandwidth [–3 dB, G = 2 (–1)]
– 100 V/µs Slew Rate
D
90 mA Output Drive (Typ)
D
Very Low Distortion
– THD = –72 dBc (f = 1 MHz, R
L
= 150 Ω)
– THD = –90 dBc (f = 1 MHz, R
L
= 1 kΩ)
D
5 V, ±5 V to ±15 V Typical Operation
D
Available in Standard SOIC or MSOP
PowerPAD Package
description
The THS6062 is a high-speed differential receiver designed for ADSL data communication systems. Its very
low 1.6 nV/√Hz
voltage noise provides the high signal-to-noise ratios necessary for the long transmission
lengths of ADSL systems over copper telephone lines. In addition, this receiver operates with a very low
distortion of –90 dBc (f = 1 MHz, R
L
= 1 kΩ), exceeding the distortion requirements of ADSL CODECs. The
THS6062 is a voltage feedback amplifier offering a high 100-MHz bandwidth and 100-V/µs slew rate and is
stable at gains of 2(–1) or greater. It operates over a wide range of power supply voltages including 5 V and ±5V
to ±15 V. This device is available in standard SOIC or MSOP PowerP AD package. The small, surface-mount,
thermally-enhanced MSOP PowerPAD package is fully compatible with automated surface-mount assembly
procedures.
_
+
1 kΩ
1 kΩ
V
I+
_
+
1 kΩ
1 kΩ
V
I–
+
–
1 kΩ
1 kΩ
2 kΩ
50 Ω
+
–
1 kΩ
1 kΩ
2 kΩ
1:1
To Telephone Line
50 Ω
Receiver 1
Receiver 2
V
O+
V
O–
100 Ω
Driver 1
Driver 2
THS6022
THS6062
Figure 1. Typical Client-Side ADSL Application
CAUTION: The THS6062 provides ESD protection circuitry. However, permanent damage can still occur if this device is subjected
to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss
of functionality.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Cross Section View Showing PowerPAD
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
–V
CC
V
CC+
2OUT
2IN–
2IN+
D AND DGN PACKAGE
(TOP VIEW)
PowerPAD is a trademark of Texas Instruments Incorporated.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY
DEVICE
DRIVER RECEIVER 5 V ±5 V ±15 V
BW
(MHz)SR(V/µs)
THD
f = 1 MHz
(dB)
I
O
(mA)
V
n
(nV/√Hz
)
THS6002
•
• • • 140 1000 –62 500 1.7
THS6012 • • • 140 1300 –65 500 1.7
THS6022 • • • 210 1900 –66 250 1.7
THS6062 • • • • 100 100 –72 90 1.6
THS7002 • • • 70 100 –84 25 2.0
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC
SMALL OUTLINE
†
(D)
PowerPAD PLASTIC
MSOP†
(DGN)
MSOP
SYMBOL
EVALUATION
MODULE
0°C to 70°C THS6062CD THS6062CDGN TIABE THS6062EVM
–40°C to 85°C THS6062ID THS6062IDGN TIABH —
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS6062CDGNR).
functional block diagram
1OUT
1IN–
1IN+
V
CC+
2OUT
2IN–
2IN+
V
CC–
–
+
–
+
1
2
3
4
5
6
7
8
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, V
CC+
to VCC– 33V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
±V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, I
O
150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
IO
±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, T
A
: C–suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, T
J
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
θ
θ
T
= 25°C
PACKAGE
JA
(°C/W)
JC
(°C/W)
A
POWER RATING
D 167
†
38.3 740 mW
DGN
‡
58.4 4.7 2.14 W
†
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
‡
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to
Application Information
section of this data sheet.
recommended operating conditions
MIN NOM MAX UNIT
pp
Dual supply ±2.5 ±16
Suppl
y v
oltage, V
CC+
and V
CC–
Single supply 5 32
V
p
p
C-suffix 0 70
°
Operating free-air temperature, T
A
I-suffix –40 85
°C
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
pp
p
Dual supply ±2.25 ±16.5
VCCSuppl
y v
oltage operating range
Single supply 4.5 33
V
TA = 25°C 8.5 10
V
CC
=
±15 V
TA = full range 11
pp
p
p
TA = 25°C 7.5 9
ICCSupply current (per amplifier)
V
CC
= ±5
V
TA = full range 10.5
mA
TA = 25°C 7.3 9
V
CC
= ±2.5
V
TA = full range 10.5
VCC = ±15 V ±13 ±13.6
VCC = ±5 V
RL = 1 kΩ
±3.4 ±3.8
p
VCC = ±2.5 V ±1 ±1.3
VOOutput voltage swing
VCC = ±15 V RL = 250 Ω ±12 ±12.9
V
VCC = ±5 V
±3 ±3.5
VCC = ±2.5 V
R
L
=
150 Ω
±0.9 ±1.2
VCC = ±15 V 60 90
I
O
Output current (see Note 1)
VCC = ±5 V
RL = 20 Ω
50 70
mA
VCC = ±2.5 V 40 55
I
SC
Short-circuit current (see Note 1) VCC = ±15 V 150 mA
p
TA = 25°C 1.5 6
VIOInput offset voltage
V
CC
= ±5 V or
±15 V
TA = full range 8
mV
Offset drift VCC = ±5 V or ±15 V TA = full range 20 µV/°C
p
TA = 25°C 3 6
IIBInput bias current
V
CC
= ±5 V or
±15 V
TA = full range 8
µ
A
p
TA = 25°C 30 250
IOSInput offset current
V
CC
=
±5 V or ±15 V
TA = full range 400
nA
Offset current drift VCC = ±5 V or ±15 V TA = full range 0.3 nA/°C
TA = 25°C 85 95
V
CC
=
±15 V
,
V
ICR
=
±12 V
TA = full range 80
CMRR
Common mode rejection ratio
TA = 25°C 90 100
dB
V
CC
=
±5 V
,
V
ICR
=
±2.5 V
TA = full range 85
pp
TA = 25°C 85 95
PSRR
Power supply rejection ratio
V
CC
= ±5 V or
±15 V
TA = full range 80
dB
†
Full range = 0°C to 70°C for the THS6062C and –40°C to 85°C for the THS6062I.
NOTE 1: Observe power dissipation ratings to keep the junction temperature below absolute maximum ratings when the output is heavily loaded
or shorted. See the absolute maximum ratings section for more information.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = ±15 V ±13.5 ±14.3
V
ICR
Common-mode input voltage range
VCC = ±5 V
±3.8 ±4.3
V
VCC = ±2.5 V ±1.4 ±1.8
R
I
Input resistance 2 MΩ
C
i
Input capacitance 1.5 pF
R
O
Output resistance Open loop 13 Ω
V
= ±15 V , V
= ±10 V ,
TA = 25°C 40 70
p
p
CC
,
O
,
RL = 1 kΩ
TA = full range 35
V/mV
Open loop gain
V
= ±5 V, V
= ±2.5 V ,
TA = 25°C 35 50
CC
,
O
,
RL = 1 kΩ
TA = full range 30
V/mV
†
Full range = 0°C to 70°C for the THS6062C and –40°C to 85°C for the THS6062I.
operating characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
VCC = ±15 V 100
SR Slew rate (see Note 2)
VCC = ±5 V
Gain = –1
80
V/µs
VCC = ±2.5 V 70
VCC = ±15 V , 5-V step 60
Settling time to 0.1%
VCC = ±5 V, 2.5-V step
Gain = –1
45
ns
VCC = ±2.5 V , 1-V step 35
t
s
VCC = ±15 V , 5-V step 90
Settling time to 0.01%
VCC = ±5 V, 2.5-V step
Gain = –1
80
ns
VCC = ±2.5 V , 1-V step 75
VCC = ±5 V or ±15 V,
RL = 150 Ω –72
THD
Total harmonic distortion
V
O(pp)
= 2 V,
f
= 1 MHz,
Gain = 2
RL = 1 kΩ –90
dBc
V
n
Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 1.6 nV/√Hz
I
n
Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 1.2 pA/√Hz
VCC = ±15 V
100
Dynamic performance small-signal
–
VCC = ±5 V
V
O(pp)
= 0.4 V,
–
90
bandwidth (–3 dB)
VCC = ±2.5 V
Gain = 2
, –
1
85
VCC = ±15 V
50
MH
z
Bandwidth for 0.1 dB flatness
VCC = ±5 V
V
O(pp)
= 0.4 V,
–
45
BW
VCC = ±2.5 V
Gain = 2
, –
1
40
p
V
O(pp)
= 20 V,
VCC = ±15 V
1.6
Full power bandwidth (see Note 3)
V
O(pp)
= 5 V,
VCC = ±5 V
R
L
=
1 kΩ
5
MH
z
Channel-to-channel crosstalk
VCC = ±5 V or ±15 V, f = 1 MHz,
Gain = 2
–61 dBc
†
Full range = 0°C to 70°C for the THS6062C and –40°C to 85°C for the THS6062I.
NOTES: 2. Slew rate is measured from an output level range of 25% to 75%.
3. Full power bandwidth = slew rate /2 π V
(peak)
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
_
+
330 Ω
50 Ω
150 Ω
V
O1
V
I1
330 Ω
CH1
_
+
330 Ω
50 Ω
150 Ω
V
O2
V
I2
330 Ω
CH2
Figure 2. THS6062 Crosstalk Test Circuit
_
+
R
g
R
f
50 Ω
R
L
V
O
V
I
Figure 3. Step Response Test Circuit
_
+
R
g
R
f
50 Ω
R
L
V
O
V
I
Figure 4. Step Response Test Circuit
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
IO
Input offset voltage vs Free-air temperature 5
I
IB
Input bias current vs Free-air temperature 6
V
O
Output voltage vs Supply voltage 7
Maximum output voltage swing vs Free-air temperature 8
I
O
Maximum output current vs Free-air temperature 9
I
CC
Supply current vs Free-air temperature 10
V
IC
Common-mode input voltage vs Supply voltage 11
Z
O
Closed-loop output impedance vs Frequency 12
Open-loop gain 13
Phase response 13
PSRR Power-supply rejection ratio vs Frequency 14
CMRR Common-mode rejection ratio vs Frequency 15
Crosstalk vs Frequency 16
Harmonic distortion vs Frequency 17, 18
Harmonic distortion vs Peak-to-peak output voltage 19, 20
SR Slew rate vs Free-air temperature 21
0.1% settling time vs Output voltage step size 22
Output amplitude vs Frequency 23–29
Small and large frequency response 30–33
1-V step response 34, 35
4-V step response 36
20-V step response 37
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
VCC = ± 5 V
VCC = ± 15 V
–1.5
–1.6
–1.7
–1.8
–40 –20 0 20
– Input Offset Voltage – mV
–1.4
–1.3
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
–1.2
40 100
60
80
TA – Free-Air Temperature – °C
V
IO
Figure 6
2.90
2.85
2.80
2.70
–40 –20 0 20 40
– Input Bias Current – mA
3
3.05
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
3.10
60 80 100
2.95
2.75
TA – Free-Air Temperature – °C
I
IB
VCC = ± 15 V
VCC = ± 5 V
Figure 7
6
4
2
0
246 810
– Output Voltage Swing – V
10
12
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
12 14 16
8
TA = 25°C
RL = 1 kΩ
RL = 150 Ω
V
O
||
± VCC – Supply Voltage – ± V
Figure 8
12
4.5
3.5
2.5
–40 –20 0 20 40
Maximum Output Voltage Swing –
13
13.5
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE–AIR TEMPERATURE
14
60 80 100
12.5
4
3
VCC = ± 5 V
RL = 150 Ω
VCC = ± 5 V
RL = 1 kΩ
TA – Free-Air Temperature – °C
VCC = ± 15 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
±V
2
1.5
1
VCC = ± 2.5 V
RL = 150 Ω
VCC = ± 2.5 V
RL = 1 kΩ
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
80
70
60
50
–40 –20 0 20 40
– Maximum Output Current – mA
90
100
MAXIMUM OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
110
60 80 100
TA – Free-Air Temperature –°C
I
O
VCC = ± 15 V
Sink Current
VCC = ± 15 V
Source Current
VCC = ± 5 V
Sink Current
VCC = ± 5 V
Source Current
RL = 20 Ω
VCC = ± 2.5 V
Source Current
VCC = ± 2.5 V
Sink Current
Figure 10
8
7
6
5
–40 –20 0 20 40
– Supply Current – mA
9
10
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
11
60 80 100
TA – Free-Air Temperature – °C
I
CC
VCC = ± 10 V
VCC = ± 5 V
VCC = ± 2.5 V
VCC = ± 15 V
Figure 11
± VCC – Supply Voltage – ± V
TA = 25°C
7.5
5
2.5
0
0 2.5 5 7.5
– Common-Mode Input Voltage – V
10
12.5
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
10 12.5 15
V
IC
±
Figure 12
1
0.1
0.01
100 k 1 M
– Closed-Loop Output Impedance –
10
f – Frequency – Hz
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
100
100 M 500 M
10 M
Z
O
Ω
Gain = 1
RF = 1 kΩ
PI = + 3 dBm
V
O
+
–
50 Ω
1 kΩ
1 kΩ
V
I
THS6062
(
V
O
V
I
=
1000
Z
o
)
– 1
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
40
20
0
–20
100 1 k 10 k 100 k 1 M
Open-Loop Gain – dB
60
80
f – Frequency – Hz
OPEN-LOOP GAIN AND PHASE RESPONSE
100
10 M 100 M 1 G
Gain
Phase
VCC = ± 15 V
RL = 150 Ω
Phase Response
0°
–45°
–90°
45°
–135°
–180°
–225°
Figure 13
Figure 14
V
CC+
V
CC–
VCC = ± 15 V and ± 5 V
60
40
20
0
10 100 1 k 10 k 100 k
PSRR – Power-Supply Rejection Ratio – dB
80
100
f – Frequency – Hz
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
120
1 M 10 M 100 M
Figure 15
_
+
1 kΩ
1 kΩ
1 kΩ
1 kΩ R
L
150 Ω
V
O
V
I
60
40
20
0
10 100 1 k 10 k 100 k
CMRR – Common-Mode Rejection Ratio – dB
80
100
f – Frequency – Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
1 M 10 M 100 M
VCC = ± 15 V
VCC = ± 5 V
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Input = CH 2
Output = CH 1
Input = CH 1
Output = CH 2
VCC = ± 15 V
PI = 0 dBm
See Figure 1
–30
–60
–70
–90
100 k 1 M 10 M
Crosstalk – dB
–20
–10
f – Frequency – Hz
0
100 M 500 M
–40
–50
–80
CROSSTALK
vs
FREQUENCY
Figure 16
Figure 17
–70
–80
–100
–110
100 k 1 M
Harmonic Distortion – dBc
–60
–50
f – Frequency – Hz
HARMONIC DISTORTION
vs
FREQUENCY
–40
10 M
–90
Second Harmonic
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 1 kΩ
V
O(PP)
= 2 V
Third Harmonic
Figure 18
–70
–80
–100
–110
100 k 1 M
Harmonic Distortion – dBc
–60
–50
f – Frequency – Hz
HARMONIC DISTORTION
vs
FREQUENCY
–40
10 M
–90
Second Harmonic
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
V
O(PP)
= 2 V
Third Harmonic
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 19
Second Harmonic
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 1 kΩ
f = 1 MHz
Third Harmonic
–80
–90
–100
–110
024681012
Harmonic Distortion – dBc
–70
–60
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
–50
14 16 18 20
V
O(PP)
– Peak-to-Peak Output Voltage – V
Figure 20
Second Harmonic
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 150 Ω
f = 1 MHz
Third Harmonic
–80
–90
–100
–110
024681012
Harmonic Distortion – dBc
–70
–60
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
–50
14 16 18 20
V
O(PP)
– Peak-to-Peak Output Voltage – V
–40
–30
–20
–10
Figure 21
TA – Free-Air Temperature – °C
Gain = –1
RL = 150 Ω
VCC = ± 2.5 V
Step = 2 V
VCC = ± 5 V
Step = 4 V
VCC = ± 15 V
Step = 20 V
90
70
60
40
–40 –20 0 20 40
SR – Slew Rate –
100
110
SLEW RATE
vs
FREE-AIR TEMPERATURE
120
60 80 100
80
50
sµ
V/
Figure 22
VCC = ± 2.5 V
VCC = ± 15 V
VCC = ± 5 V
Gain = –1
RF = 430 Ω
50
40
10
0
12 3
– 0.1% Settling Time – ns
60
70
0.1% SETTLING TIME
vs
OUTPUT VOLTAGE STEP SIZE
80
45
30
20
t
s
VO – Output Voltage Step Size – V
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
3
2
1
–1
100 k 1 M 10 M
Output Amplitude – dB
5
7
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
8
100 M 500 M
6
4
0
VCC = ± 15 V
Gain = 2
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 300 Ω
RF = 100 Ω
Figure 24
3
2
1
–1
100 k 1 M 10 M
Output Amplitude – dB
5
7
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
8
100 M 500 M
6
4
0
VCC = ± 5 V
Gain = 2
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 300 Ω
RF = 100 Ω
Figure 25
3
2
1
–1
100 k 1 M 10 M
Output Amplitude – dB
5
7
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
8
100 M 500 M
6
4
0
VCC = ± 2.5 V
Gain = 2
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 300 Ω
RF = 100 Ω
Figure 26
–3
–4
–5
–7
100 k 1 M 10 M
Output Amplitude – dB
–1
1
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
2
100 M 500 M
0
–2
–6
VCC = ± 15 V
Gain = –1
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 360 Ω
RF = 100 Ω
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 27
–3
–4
–5
–7
100 k 1 M 10 M
Output Amplitude – dB
–1
1
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
2
100 M 500 M
0
–2
–6
VCC = ± 5 V
Gain = –1
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 360 Ω
RF = 100 Ω
Figure 28
–3
–4
–5
–7
100 k 1 M 10 M
Output Amplitude – dB
–1
1
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
2
100 M 500 M
0
–2
–6
VCC = ± 2.5 V
Gain = –1
RL = 150 Ω
V
O(PP)
= 0.4 V
RF = 1 kΩ
RF = 360 Ω
RF = 100 Ω
10
6
4
0
100 k 1 M 10 M
Output Amplitude – dB
12
14
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
16
100 M 500 M
8
2
VCC = ± 15 V
VCC = ± 2.5 V
Gain = 5
RF = 3.9 kΩ
RL = 150 Ω
V
O(PP)
= 0.4 V
Figure 29
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 30
–12
–15
–18
–24
100 k 1 M 10 M
– Output Voltage Level – dBV
–6
0
f – Frequency – Hz
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
3
100 M 500 M
–3
–9
–21
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL= 150 Ω
VI = 0.5 V RMS
VI = 0.25 V RMS
VI = 125 mV RMS
VI = 62.5 mV RMS
V
O
Figure 31
–12
–15
–18
–24
100 k 1 M 10 M
– Output Voltage Level – dBV
–6
0
f – Frequency – Hz
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
3
100 M 500 M
–3
–9
–21
VCC = ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
VI = 0.5 V RMS
VI = 0.25 V RMS
VI = 125 mV RMS
VI = 62.5 mV RMS
V
O
Figure 32
18
–21
–24
–30
100 k 1 M 10 M
– Output Voltage Level – dBV
–12
–6
f – Frequency – Hz
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
–3
100 M 500 M
–9
–15
–27
VCC = ± 15 V
Gain = –1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
VI = 0.25 V RMS
VI = 125 mV RMS
VI = 62.5 mV RMS
V
O
Figure 33
18
–21
–24
–30
100 k 1 M 10 M
– Output Voltage Level – dBV
–12
–6
f – Frequency – Hz
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
–3
100 M 500 M
–9
–15
–27
VCC = ± 5 V
Gain = –1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
VI = 0.25 V RMS
VI = 125 mV RMS
VI = 62.5 mV RMS
V
O
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 34
0
–0.2
–0.4
–0.6
0 50 100 150
– Output Voltage – V
0.2
0.4
t – Time – ns
1-V STEP RESPONSE
0.6
200 250
V
O
VCC = ± 2.5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 2
300
Figure 35
0
–0.2
–0.4
–0.6
0 200 400 600
– Output Voltage – V
0.2
0.4
t – Time – ns
1-V STEP RESPONSE
0.6
800 1000
V
O
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 2
Figure 36
0
–0.5
–1.5
–2.5
0 200 400 600
– Output Voltage – V
1.5
2
t – Time – ns
4-V STEP RESPONSE
2.5
800 1000
V
O
VCC = ± 5 V
Gain = –1
RF = 430 Ω
RL = 150 Ω
See Figure 3
1
0.5
–1
–2
Figure 37
0
–5
–10
–15
0 200 400 600
– Output Voltage – V
5
10
t – Time – ns
20-V STEP RESPONSE
15
800 1000
V
O
RL = 1 kΩ
RL = 150 Ω
VCC = ± 15 V
Gain = 2
RF = 330 Ω
See Figure 2
Offset For Clarity
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation
The THS6062 is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
f
T
s of several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 38.
IN– (2,6)
IN+ (3,5)
(1,7) OUT
(4) VCC–
(7) VCC+
Figure 38. THS6062 Simplified Schematic
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The ADSL remote terminal receive band consists of 255 separate carrier frequencies each with its own
modulation and amplitude level. With such an implementation, it is imperative that signals received off the
telephone line have as high a signal-to-noise ratio (SNR) as possible. This is because of the numerous sources
of interference on the line. The best way to accomplish this high SNR is to have a low-noise receiver on the
front-end. It is also important to have the lowest distortion possible to help minimize against interference within
the ADSL carriers. The THS6062 was designed with these two priorities in mind.
By taking advantage of the superb characteristics of the complimentary bipolar process (BICOM), the THS6062
offers extremely low noise and distortion while maintaining a high bandwidth. There are some aspects that help
minimize distortion in any amplifier. The first is to extend the bandwidth of the amplifier as high as possible
without peaking. This allows the amplifier to eliminate any nonlinearities in the output signal. Another thing that
helps to minimize distortion is to increase the load impedance seen by the amplifier, thereby reducing the
currents in the output stage. This will help keep the output transistors in their linear amplification range and will
also reduce the heating effects. This can be seen in Figures 17 to 20, which show a 1-kΩ load distortion is much
better than a 150 Ω load.
One client side terminal circuit implementation, shown in Figure 39, uses a 1:2 transformer ratio. While creating
a power and output voltage advantage for the line drivers, the 1:2 transformer ratio reduces the SNR for the
received signals. The ADSL standard, ANSI T1.413, stipulates a noise power spectral density of –140 dBm/Hz,
which is equivalent to 31.6 nV/√Hz
for a 100 Ω system. Although many amplifiers can reach this level of
performance, actual ADSL system testing has indicated that the noise power spectral density may typically be
≤ –150 dBm/Hz, or ≤ 10 nV/√Hz
. With a transformer ratio of 1:2, this number reduces to less than 5 nV/√Hz.
The THS6062, with an equivalent input noise of 1.6 nV/√Hz
, is an excellent choice for this application. Coupled
with a very low 1.2 pA/√Hz
equivalent input current noise and low value resistors, the THS6062 will ensure that
the received signal SNR will be as high as possible.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
_
+
6.8 µF0.1 µF
–6 V
6.8 µF0.1 µF
6 V
1 kΩ
1 kΩ
+
+
V
I+
_
+
6.8 µF0.1 µF
–6 V
6.8 µF0.1 µF
6 V
1 kΩ
1 kΩ
+
+
V
I–
+
–
499 Ω
499 Ω
1 kΩ
12.5 Ω
+
–
499 Ω
0.1 µF
499 Ω
1 kΩ
1:2
Telephone Line
12.5 Ω
6 V
–6 V
0.01 µF
THS6062
Receiver 1
THS6062
Receiver 2
V
O+
V
O–
THS6022
Driver 1
THS6022
Driver 2
100 Ω
Driver Block
Receiver Block
Figure 39. THS6062 Client-Side ADSL Application
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown
in Figure 40. This model includes all of the noise sources as follows:
• e
n
= amplifier internal voltage noise (nV/√Hz)
• IN+ = noninverting current noise (pA/√Hz)
• IN– = inverting current noise (pA/√Hz)
• e
Rx
= thermal voltage noise associated with each resistor (eRx = 4 kTRx)
_
+
R
F
R
S
R
G
e
Rg
e
Rf
e
Rs
e
n
IN+
Noiseless
IN–
e
ni
e
no
Figure 40. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
eni+
ǒ
e
n
Ǔ
2
)
ǒ
IN
)
R
S
Ǔ
2
)
ǒ
IN–
ǒRFø
R
G
Ǔ
Ǔ
2
)
4kTRs)
4kT
ǒ
RFø
R
G
Ǔ
Ǹ
Where:
k = Boltzmann’s constant = 1.380658 × 10
–23
T = temperature in degrees Kelvin (273 +°C)
R
F
|| RG = parallel resistance of RF and R
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (A
V
).
eno+
eniAV+
e
ni
ǒ
1
)
R
F
R
G
Ǔ
(Noninverting Case)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R
G
), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R
S
) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
noise calculations and noise figure (continued)
For more information on noise analysis, please refer to the
Noise Analysis
section in
Operational Amplifier
Circuits Applications Report
(literature number SLVA043).
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF+10log
ȧ
ȧ
ȱ
Ȳ
e
2
ni
ǒ
e
Rs
Ǔ
2
ȧ
ȧ
ȳ
ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate the noise figure as:
NF+10log
ȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1
)
ȧ
ȡ
Ȣ
ǒ
e
n
Ǔ
2
)
ǒ
IN
)
R
S
Ǔ
2
ȧ
ȣ
Ȥ
4kTR
S
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
Figure 40 shows the noise figure graph for the THS6062.
10
6
2
0
10 100
Noise Figure – dB
12
14
NOISE FIGURE
vs
SOURCE RESISTANCE
16
1 k 10 k
8
4
Source Resistance – Ω
f = 10 kHz
TA = 25°C
Figure 41. Noise Figure vs Source Resistance
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
optimizing frequency response
Internal frequency compensation of the THS6062 was selected to provide very wide bandwidth performance
and still maintain a very low noise floor. In order to meet these performance requirements, the THS6062 must
have a minimum gain of 2 (–1). Because everything is referred to the noninverting terminal of an operational
amplifier, the noise gain in a G = –1 configuration is the same as in a G = 2 configuration.
One of the keys to maintaining a smooth frequency response, and hence, a stable pulse response, is to pay
particular attention to the inverting terminal. Any stray capacitance at this node causes peaking in the frequency
response (see Figure 42 and Figure 43). There are two things that can be done to help minimize this effect. The
first is to simply remove any ground planes under the inverting terminal of the amplifier. This also includes the
trace that connects to this terminal. Additionally , the length of this trace should be minimized. The capacitance
at this node causes a lag in the voltage being fed back due to the charging and discharging of the stray
capacitance. If this lag becomes too long, the amplifier will not be able to correctly keep the noninverting terminal
voltage at the same potential as the inverting terminal’s voltage. Peaking and possibly oscillations will then
occur.
Figure 42
_
+
150 Ω
V
O
V
I
50 Ω
C
IN–
300 Ω
7
6
2
0
100 k 1 M 10 M
Output Amplitude – dB
8
9
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
10
100 M 500 M
5
4
3
1
C
IN–
= 10 pF
No C
IN–
(Stray C Only)
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
V
O(PP)
= 0.4 V
300 Ω
Figure 43
_
+
360 Ω
150 Ω
V
O
V
I
56 Ω
C
IN–
360 Ω
1
0
–4
–6
100 k 1 M 10 M
Output Amplitude – dB
2
3
f – Frequency – Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
4
100 M 500 M
–1
–2
–3
–5
C
IN–
= 10 pF
No C
IN–
(Stray C Only)
VCC = ± 15 V
Gain = –1
RF = 360 Ω
RL = 150 Ω
V
O(PP)
= 0.4 V
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
optimizing frequency response (continued)
The next thing that helps to maintain a smooth frequency response is to keep the feedback resistor (Rf) and
the gain resistor (R
g
) values fairly low. These two resistors are effectively in parallel when looking at the ac
small-signal response. This is why in Figure 29, a feedback resistor of 3.9 kΩ with a gain resistor of 1 kΩ only
shows a small peaking in the frequency response. The parallel resistance is only 800 Ω. This value, in
conjunction with a very small stray capacitance test PCB, forms a zero on the edge of the amplifier’s natural
frequency response. To eliminate this peaking, all that needs to be done is to reduce the feedback and gain
resistances. One other way to compensate for this stray capacitance is to add a small capacitor in parallel with
the feedback resistor. This helps to neutralize the ef fects of the stray capacitance. To keep this zero out of the
operating range, the stray capacitance and resistor value’s time constant must be kept low . But, as can be seen
in Figures 23 – 28, a value too low starts to reduce the bandwidth of the amplifier. Table 1 shows some
recommended feedback resistors to be used with the THS6062.
Table 1. Recommended Feedback Resistors
GAIN Rf for VCC = ±15 V , ± 5 V, 5 V
2 300 Ω
–1 360 Ω
5 3.3 kΩ (low stray-c PCB only)
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6062 has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 44. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
+
_
THS6062
C
LOAD
360 Ω
Input
Output
360 Ω
20 Ω
Figure 44. Driving a Capacitive Load
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula are used to calculate the output offset voltage:
VOO+
V
IO
ǒ
1
) ǒ
R
F
R
G
Ǔ
Ǔ
"
I
IB
)
R
S
ǒ
1
) ǒ
R
F
R
G
Ǔ
Ǔ
"
I
IB–RF
+
–
V
I
+
R
G
R
S
R
F
I
IB–
V
O
I
IB+
Figure 45. Output Offset Voltage Model
circuit layout considerations
In order to achieve the high-frequency performance of the THS6062, it is essential that proper printed-circuit
board high frequency design techniques be followed. A general set of guidelines is given below. In addition, a
THS6062 evaluation board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations
The THS6062 is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerP AD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 46(a) and Figure 46(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 45(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerP AD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 46. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 47. PowerPAD PCB Etch and Via Pattern
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations
1. Prepare the PCB with a top side etch pattern as shown in Figure 47. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept
small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS6062DGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS6062DGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS6062DGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
The actual thermal performance achieved with the THS6062DGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ
JA
, is about 58.4°C/W. For comparison, the non-PowerPAD version of
the THS6062 IC (SOIC) is shown. For a given θ
JA
, the maximum power dissipation is shown in Figure 48 and
is calculated by the following formula:
PD+
ǒ
T
MAX–TA
q
JA
Ǔ
Where:
P
D
= Maximum power dissipation of THS6062 IC (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
T
A
= Free-ambient air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θJC= Thermal coefficient from junction to case
θ
CA
= Thermal coefficient from case to ambient air (°C/W)
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θJA = 98°C/W
TJ = 150°C
SOIC Package
Low-K Test PCB
θJA = 167°C/W
2
1.5
1
0
–40 –20 0 20 40
Maximum Power Dissipation – W
2.5
3
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
60 80 100
0.5
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 48. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerP AD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced Package.
This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
The next thing that should be considered is the package constraints. The two sources of heat within an amplifier
are quiescent power and output power. The designer should never forget about the quiescent heat generated
within the device, especially a multiamplifier device. Because these devices have linear output stages (Class
A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 49 and Figure 50
show this effect, along with the quiescent heat, with an ambient air temperature of 50°C. When using
V
CC
= 5 V or ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using
V
CC
= ±15 V , the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor
when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ
JA
decreases
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package. Because the THS6062 is a dual amplifier, the sum of the RMS output currents and voltages should
be used to choose the proper package.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Figure 49
Package With
θJA < = 110°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ± 5 V
Tj = 150°C
TA = 50°C
100
80
40
0
012 3
– Maximum RMS Output Current – mA
140
180
200
45
160
120
60
20
| VO | – RMS Output Voltage – V
I
O
||
Maximum Output
Current Limit Line
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Figure 50
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
SO-8 Package
θJA = 98°C/W
High-K Test PCB
TJ = 150°C
TA = 50°C
| VO | – RMS Output Voltage – V
– Maximum RMS Output Current – mA
I
O
||
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
evaluation board
An evaluation board is available for the THS6062 (literature number SLOP221). This board has been configured
for very low parasitic capacitance in order to realize the full performance of the amplifier. For more information,
refer to the
THS6062 EVM User’s Guide
(literature number SLOU036) To order the evaluation board contact
your local TI sales office or distributor.
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/A 01/98
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65
M
0,25
0°–6°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1999, Texas Instruments Incorporated
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